static u_int get_page(u_int vaddr)
{
+#ifndef PCSX
u_int page=(vaddr^0x80000000)>>12;
+#else
+ u_int page=vaddr&~0xe0000000;
+ if (page < 0x1000000)
+ page &= ~0x0e00000; // RAM mirrors
+ page>>=12;
+#endif
#ifndef DISABLE_TLB
if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
#endif
alloc_reg(current,i,CSREG); // Load status
if(opcode2[i]<3) // MFC1/DMFC1/CFC1
{
- assert(rt1[i]);
- clear_const(current,rt1[i]);
- if(opcode2[i]==1) {
- alloc_reg64(current,i,rt1[i]); // DMFC1
- current->is32&=~(1LL<<rt1[i]);
- }else{
- alloc_reg(current,i,rt1[i]); // MFC1/CFC1
- current->is32|=1LL<<rt1[i];
+ if(rt1[i]){
+ clear_const(current,rt1[i]);
+ if(opcode2[i]==1) {
+ alloc_reg64(current,i,rt1[i]); // DMFC1
+ current->is32&=~(1LL<<rt1[i]);
+ }else{
+ alloc_reg(current,i,rt1[i]); // MFC1/CFC1
+ current->is32|=1LL<<rt1[i];
+ }
+ dirty_reg(current,rt1[i]);
}
- dirty_reg(current,rt1[i]);
alloc_reg_temp(current,i,-1);
}
else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
//if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
//assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
- if(ooo)
+ if(ooo) {
if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
- {
- // Write-after-read dependency prevents out of order execution
- // First test branch condition, then execute delay slot, then branch
- ooo=0;
+ {
+ // Write-after-read dependency prevents out of order execution
+ // First test branch condition, then execute delay slot, then branch
+ ooo=0;
+ }
+ if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))
+ // BxxZAL $ra is available to delay insn, so do it in order
+ ooo=0;
}
if(ooo) {
load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
if(rt1[i]==31) {
int rt,return_address;
- assert(rt1[i+1]!=31);
- assert(rt2[i+1]!=31);
rt=get_reg(branch_regs[i].regmap,31);
assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
if(rt>=0) {
int nottaken=0;
if(rt1[i]==31) {
int rt,return_address;
- assert(rt1[i+1]!=31);
- assert(rt2[i+1]!=31);
rt=get_reg(branch_regs[i].regmap,31);
if(rt>=0) {
// Save the PC even if the branch is not taken
else ba[i]=-1;
/* Is this the end of the block? */
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
+#ifdef PCSX
+ // check for link register access in delay slot
+ int rt1_=rt1[i-1];
+ if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
+ printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
+ ba[i-1]=-1;
+ itype[i-1]=INTCALL;
+ done=2;
+ }
+ else
+#endif
if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
done=2;
}
if (rt1[i]==31) {
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
- //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
+ assert(rs1[i+1]!=31&&rs2[i+1]!=31);
assert(rt1[i+1]!=rt1[i]);
#ifdef REG_PREFETCH
alloc_reg(¤t,i,PTEMP);
if (rt1[i]!=0) {
alloc_reg(¤t,i,rt1[i]);
dirty_reg(¤t,rt1[i]);
- //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
+ assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
assert(rt1[i+1]!=rt1[i]);
#ifdef REG_PREFETCH
alloc_reg(¤t,i,PTEMP);
if (rt1[i]==31) { // BLTZAL/BGEZAL
alloc_reg(¤t,i,31);
dirty_reg(¤t,31);
- assert(rs1[i+1]!=31&&rs2[i+1]!=31);
//#ifdef REG_PREFETCH
//alloc_reg(¤t,i,PTEMP);
//#endif