#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
+#include "../gpu.h"
#include "emu_if.h"
#include "pcsxmem.h"
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
-static u8 unmapped_mem[0x1000];
+u8 zero_mem[0x1000];
u32 read_mem_dummy()
{
sioWrite8((unsigned char)(value >> 24));
}
+#ifndef DRC_DBG
+
static void map_rcnt_rcount0(u32 mode)
{
- if (mode & 0x01) { // gate
- map_item(&mem_iortab[IOMEM32(0x1100)], &psxH[0x1000], 0);
- map_item(&mem_iortab[IOMEM16(0x1100)], &psxH[0x1000], 0);
- }
- else if (mode & 0x100) { // pixel clock
+ if (mode & 0x100) { // pixel clock
map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
}
static void map_rcnt_rcount1(u32 mode)
{
- if (mode & 0x01) { // gate
- map_item(&mem_iortab[IOMEM32(0x1110)], &psxH[0x1000], 0);
- map_item(&mem_iortab[IOMEM16(0x1110)], &psxH[0x1000], 0);
- }
- else if (mode & 0x100) { // hcnt
+ if (mode & 0x100) { // hcnt
map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
}
}
}
+#else
+#define map_rcnt_rcount0(mode)
+#define map_rcnt_rcount1(mode)
+#define map_rcnt_rcount2(mode)
+#endif
+
#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
wfunc(a + 2, value >> 16);
}
+static u32 io_gpu_read_status(void)
+{
+ u32 v;
+
+ // meh2, syncing for img bit, might want to avoid it..
+ gpuSyncPluginSR();
+ v = HW_GPU_STATUS;
+
+ // XXX: because of large timeslices can't use hSyncCount, using rough
+ // approximization instead. Perhaps better use hcounter code here or something.
+ if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ v |= PSXGPU_LCF & (psxRegs.cycle << 20);
+ return v;
+}
+
+static void io_gpu_write_status(u32 value)
+{
+ GPU_writeStatus(value);
+ gpuSyncPluginSR();
+}
+
static void map_ram_write(void)
{
int i;
// default/unmapped memhandlers
for (i = 0; i < 0x100000; i++) {
//map_item(&mem_readtab[i], mem_unmrtab, 1);
- map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
+ map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
map_item(&mem_writetab[i], mem_unmwtab, 1);
}
map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
-// map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
+ map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
-// map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
// plugins might change so update the pointers
map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
- map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
for (i = 0x1c00; i < 0x1e00; i += 2)
map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
- map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
}