/******************************************************************************/
-typedef struct Rcnt
-{
- u16 mode, target;
- u32 rate, irq, counterState, irqState;
- u32 cycle, cycleStart;
-} Rcnt;
-
enum
{
Rc0Gate = 0x0001, // 0 not implemented
static const u32 FrameRate[] = { 60, 50 };
static const u32 VBlankStart[] = { 240, 256 };
static const u32 HSyncTotal[] = { 263, 313 };
-static const u32 SpuUpdInterval[] = { 23, 22 };
+static const u32 SpuUpdInterval[] = { 32, 32 };
-static const s32 VerboseLevel = 0;
+#define VERBOSE_LEVEL 0
+static const s32 VerboseLevel = VERBOSE_LEVEL;
/******************************************************************************/
-static Rcnt rcnts[ CounterQuantity ];
+Rcnt rcnts[ CounterQuantity ];
static u32 hSyncCount = 0;
static u32 spuSyncCount = 0;
+static u32 hsync_steps = 0;
+static u32 gpu_wants_hcnt = 0;
+static u32 base_cycle = 0;
u32 psxNextCounter = 0, psxNextsCounter = 0;
}
static
-void verboseLog( s32 level, const char *str, ... )
+void verboseLog( u32 level, const char *str, ... )
{
+#if VERBOSE_LEVEL > 0
if( level <= VerboseLevel )
{
va_list va;
printf( "%s", buf );
fflush( stdout );
}
+#endif
}
/******************************************************************************/
count = psxRegs.cycle;
count -= rcnts[index].cycleStart;
- count /= rcnts[index].rate;
+ if (rcnts[index].rate > 1)
+ count /= rcnts[index].rate;
if( count > 0xffff )
{
psxNextCounter = countToUpdate;
}
}
+
+ psxRegs.interrupt |= (1 << PSXINT_RCNT);
+ new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}
/******************************************************************************/
{
count = psxRegs.cycle;
count -= rcnts[index].cycleStart;
- count /= rcnts[index].rate;
+ if (rcnts[index].rate > 1)
+ count /= rcnts[index].rate;
count -= rcnts[index].target;
}
else
{
count = psxRegs.cycle;
count -= rcnts[index].cycleStart;
- count /= rcnts[index].rate;
+ if (rcnts[index].rate > 1)
+ count /= rcnts[index].rate;
count -= 0xffff;
_psxRcntWcount( index, count );
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
- psxRcntReset( 3 );
+ u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
+ u32 next_vsync, next_lace;
- spuSyncCount++;
- hSyncCount++;
+ spuSyncCount += hsync_steps;
+ hSyncCount += hsync_steps;
// Update spu.
if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
// VSync irq.
if( hSyncCount == VBlankStart[Config.PsxType] )
{
- GPU_vBlank( 1, &hSyncCount );
+ GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
// For the best times. :D
//setIrq( 0x01 );
{
hSyncCount = 0;
- GPU_vBlank( 0, &hSyncCount );
+ GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
setIrq( 0x01 );
EmuUpdate();
GPU_updateLace();
}
+
+ // Schedule next call, in hsyncs
+ hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
+ next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
+ next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
+ if( next_vsync && next_vsync < hsync_steps )
+ hsync_steps = next_vsync;
+ if( next_lace && next_lace < hsync_steps )
+ hsync_steps = next_lace;
+ if( gpu_wants_hcnt )
+ hsync_steps = 1;
+
+ rcnts[3].cycleStart = cycle - leftover_cycles;
+ if (Config.PsxType)
+ // 20.12 precision, clk / 50 / 313 ~= 2164.14
+ base_cycle += hsync_steps * 8864320;
+ else
+ // clk / 60 / 263 ~= 2146.31
+ base_cycle += hsync_steps * 8791293;
+ rcnts[3].cycle = base_cycle >> 12;
+ base_cycle &= 0xfff;
+ psxRcntSet();
}
+#ifndef NDEBUG
DebugVSync();
+#endif
}
/******************************************************************************/
{
verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
- psxRcntUpdate();
-
_psxRcntWcount( index, value );
psxRcntSet();
}
{
verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
- psxRcntUpdate();
-
rcnts[index].mode = value;
rcnts[index].irqState = 0;
{
verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
- psxRcntUpdate();
-
rcnts[index].target = value;
_psxRcntWcount( index, _psxRcntRcount( index ) );
{
u32 count;
- psxRcntUpdate();
-
count = _psxRcntRcount( index );
// Parasite Eve 2 fix.
{
u16 mode;
- psxRcntUpdate();
-
mode = rcnts[index].mode;
rcnts[index].mode &= 0xe7ff;
hSyncCount = 0;
spuSyncCount = 0;
+ hsync_steps = 1;
psxRcntSet();
}
gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
+ if (Mode == 0)
+ hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
+
+ base_cycle = 0;
+
return 0;
}