static const u32 CountToTarget = 1;
static const u32 FrameRate[] = { 60, 50 };
-static const u32 VBlankStart[] = { 240, 256 };
static const u32 HSyncTotal[] = { 263, 313 };
static const u32 SpuUpdInterval[] = { 32, 32 };
+#define VBlankStart 240
#define VERBOSE_LEVEL 0
static const s32 VerboseLevel = VERBOSE_LEVEL;
}
else
{
- rcnts[index].cycle = 0xffff * rcnts[index].rate;
+ rcnts[index].cycle = 0x10000 * rcnts[index].rate;
rcnts[index].counterState = CountToOverflow;
}
}
if (rcnts[index].rate > 1)
count /= rcnts[index].rate;
- if( count > 0xffff )
+ if( count > 0x10000 )
{
- verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
- count &= 0xffff;
+ verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
}
+ count &= 0xffff;
return count;
}
static
void psxRcntReset( u32 index )
{
- u32 count;
+ u32 rcycles;
+
+ rcnts[index].mode |= RcUnknown10;
if( rcnts[index].counterState == CountToTarget )
{
+ rcycles = psxRegs.cycle - rcnts[index].cycleStart;
if( rcnts[index].mode & RcCountToTarget )
{
- count = psxRegs.cycle;
- count -= rcnts[index].cycleStart;
- if (rcnts[index].rate > 1)
- count /= rcnts[index].rate;
- count -= rcnts[index].target;
+ rcycles -= rcnts[index].target * rcnts[index].rate;
+ rcnts[index].cycleStart = psxRegs.cycle - rcycles;
}
else
{
- count = _psxRcntRcount( index );
+ rcnts[index].cycle = 0x10000 * rcnts[index].rate;
+ rcnts[index].counterState = CountToOverflow;
}
- _psxRcntWcount( index, count );
-
if( rcnts[index].mode & RcIrqOnTarget )
{
if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
{
- verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
+ verboseLog( 3, "[RCNT %i] irq\n", index );
setIrq( rcnts[index].irq );
rcnts[index].irqState = 1;
}
}
rcnts[index].mode |= RcCountEqTarget;
+
+ if( rcycles < 0x10000 * rcnts[index].rate )
+ return;
}
- else if( rcnts[index].counterState == CountToOverflow )
+
+ if( rcnts[index].counterState == CountToOverflow )
{
- count = psxRegs.cycle;
- count -= rcnts[index].cycleStart;
- if (rcnts[index].rate > 1)
- count /= rcnts[index].rate;
- count -= 0xffff;
+ rcycles = psxRegs.cycle - rcnts[index].cycleStart;
+ rcycles -= 0x10000 * rcnts[index].rate;
+
+ rcnts[index].cycleStart = psxRegs.cycle - rcycles;
- _psxRcntWcount( index, count );
+ if( rcycles < rcnts[index].target * rcnts[index].rate )
+ {
+ rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
+ rcnts[index].counterState = CountToTarget;
+ }
if( rcnts[index].mode & RcIrqOnOverflow )
{
if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
{
- verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
+ verboseLog( 3, "[RCNT %i] irq\n", index );
setIrq( rcnts[index].irq );
rcnts[index].irqState = 1;
}
rcnts[index].mode |= RcOverflow;
}
-
- rcnts[index].mode |= RcUnknown10;
-
- psxRcntSet();
}
void psxRcntUpdate()
}
// VSync irq.
- if( hSyncCount == VBlankStart[Config.PsxType] )
+ if( hSyncCount == VBlankStart )
{
- if( !(HW_GPU_STATUS & PSXGPU_ILACE) )
- HW_GPU_STATUS |= PSXGPU_LCF;
-
+ HW_GPU_STATUS &= ~PSXGPU_LCF;
+ GPU_vBlank( 1, 0 );
setIrq( 0x01 );
EmuUpdate();
hSyncCount = 0;
frame_counter++;
- HW_GPU_STATUS &= ~PSXGPU_LCF;
- if( HW_GPU_STATUS & PSXGPU_ILACE )
+ gpuSyncPluginSR();
+ if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
HW_GPU_STATUS |= frame_counter << 31;
+ GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
}
// Schedule next call, in hsyncs
hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
- next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
+ next_vsync = VBlankStart - hSyncCount; // ok to overflow
next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
if( next_vsync && next_vsync < hsync_steps )
hsync_steps = next_vsync;
base_cycle += hsync_steps * 8791293;
rcnts[3].cycle = base_cycle >> 12;
base_cycle &= 0xfff;
- psxRcntSet();
}
+ psxRcntSet();
+
#ifndef NDEBUG
DebugVSync();
#endif