#include "psxcounters.h"
#include "gpu.h"
-#include "debug.h"
+//#include "debug.h"
+#define DebugVSync()
/******************************************************************************/
static const u32 CountToTarget = 1;
static const u32 FrameRate[] = { 60, 50 };
-static const u32 HSyncTotal[] = { 263, 313 };
-static const u32 SpuUpdInterval[] = { 32, 32 };
+static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
#define VBlankStart 240
#define VERBOSE_LEVEL 0
-static const s32 VerboseLevel = VERBOSE_LEVEL;
/******************************************************************************/
-
+#ifdef DRC_DISABLE
Rcnt rcnts[ CounterQuantity ];
-
+#endif
u32 hSyncCount = 0;
u32 frame_counter = 0;
-static u32 spuSyncCount = 0;
static u32 hsync_steps = 0;
-static u32 base_cycle = 0;
u32 psxNextCounter = 0, psxNextsCounter = 0;
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
- if( level <= VerboseLevel )
+ if( level <= VERBOSE_LEVEL )
{
va_list va;
char buf[ 4096 ];
}
}
+static void scheduleRcntBase(void)
+{
+ // Schedule next call, in hsyncs
+ if (hSyncCount < VBlankStart)
+ hsync_steps = VBlankStart - hSyncCount;
+ else
+ hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
+
+ if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
+ {
+ rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
+ }
+ else
+ {
+ // clk / 50 / 314 ~= 2157.25
+ // clk / 60 / 263 ~= 2146.31
+ u32 mult = Config.PsxType ? 8836089 : 8791293;
+ rcnts[3].cycle = hsync_steps * mult >> 12;
+ }
+}
+
void psxRcntUpdate()
{
u32 cycle;
cycle = psxRegs.cycle;
// rcnt 0.
- if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
+ while( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
{
psxRcntReset( 0 );
}
// rcnt 1.
- if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
+ while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
{
psxRcntReset( 1 );
}
// rcnt 2.
- if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
+ while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
{
psxRcntReset( 2 );
}
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
- u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
- u32 next_vsync, next_lace;
-
- spuSyncCount += hsync_steps;
hSyncCount += hsync_steps;
- // Update spu.
- if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
- {
- spuSyncCount = 0;
-
- if( SPU_async )
- {
- SPU_async( cycle, 1 );
- }
- }
-
// VSync irq.
if( hSyncCount == VBlankStart )
{
- HW_GPU_STATUS &= ~PSXGPU_LCF;
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
GPU_vBlank( 1, 0 );
setIrq( 0x01 );
EmuUpdate();
GPU_updateLace();
+
+ if( SPU_async )
+ {
+ SPU_async( cycle, 1 );
+ }
}
// Update lace. (with InuYasha fix)
if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
{
+ rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
hSyncCount = 0;
frame_counter++;
gpuSyncPluginSR();
- if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
- HW_GPU_STATUS |= frame_counter << 31;
- GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
+ if ((HW_GPU_STATUS & SWAP32(PSXGPU_ILACE_BITS)) == SWAP32(PSXGPU_ILACE_BITS))
+ HW_GPU_STATUS |= SWAP32(frame_counter << 31);
+ GPU_vBlank(0, SWAP32(HW_GPU_STATUS) >> 31);
}
- // Schedule next call, in hsyncs
- hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
- next_vsync = VBlankStart - hSyncCount; // ok to overflow
- next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
- if( next_vsync && next_vsync < hsync_steps )
- hsync_steps = next_vsync;
- if( next_lace && next_lace < hsync_steps )
- hsync_steps = next_lace;
-
- rcnts[3].cycleStart = cycle - leftover_cycles;
- if (Config.PsxType)
- // 20.12 precision, clk / 50 / 313 ~= 2164.14
- base_cycle += hsync_steps * 8864320;
- else
- // clk / 60 / 263 ~= 2146.31
- base_cycle += hsync_steps * 8791293;
- rcnts[3].cycle = base_cycle >> 12;
- base_cycle &= 0xfff;
+ scheduleRcntBase();
}
psxRcntSet();
}
hSyncCount = 0;
- spuSyncCount = 0;
hsync_steps = 1;
psxRcntSet();
s32 psxRcntFreeze( void *f, s32 Mode )
{
+ u32 spuSyncCount = 0;
u32 count;
s32 i;
- gzfreeze( &rcnts, sizeof(rcnts) );
+ gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
gzfreeze( &hSyncCount, sizeof(hSyncCount) );
gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
if (Mode == 0)
{
// don't trust things from a savestate
+ rcnts[3].rate = 1;
for( i = 0; i < CounterQuantity; ++i )
{
_psxRcntWmode( i, rcnts[i].mode );
count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
_psxRcntWcount( i, count );
}
- hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
+ scheduleRcntBase();
psxRcntSet();
-
- base_cycle = 0;
}
return 0;
}
/******************************************************************************/
+// vim:ts=4:shiftwidth=4:expandtab