void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
u16 *ptr;
- u32 size;
+ u32 words;
switch (chcr) {
case 0x01000201: //cpu to spu transfer
#endif
break;
}
- SPU_writeDMAMem(ptr, (bcr >> 16) * (bcr & 0xffff) * 2);
- SPUDMA_INT((bcr >> 16) * (bcr & 0xffff) / 2);
+ words = (bcr >> 16) * (bcr & 0xffff);
+ SPU_writeDMAMem(ptr, words * 2, psxRegs.cycle);
+ HW_DMA4_MADR = SWAPu32(madr + words * 4);
+ SPUDMA_INT(words / 2);
return;
case 0x01000200: //spu to cpu transfer
#endif
break;
}
- size = (bcr >> 16) * (bcr & 0xffff) * 2;
- SPU_readDMAMem(ptr, size);
- psxCpu->Clear(madr, size);
- break;
+ words = (bcr >> 16) * (bcr & 0xffff);
+ SPU_readDMAMem(ptr, words * 2, psxRegs.cycle);
+ psxCpu->Clear(madr, words);
+
+ HW_DMA4_MADR = SWAPu32(madr + words * 4);
+ SPUDMA_INT(words / 2);
+ return;
#ifdef PSXDMA_LOG
default:
// next 32-bit pointer
addr = psxMu32( addr & ~0x3 ) & 0xffffff;
size += 1;
- } while (addr != 0xffffff);
+ } while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF
+ // any pointer with bit 23 set will do.
return size;
}
void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
u32 *ptr;
+ u32 words;
u32 size;
switch (chcr) {
break;
}
// BA blocks * BS words (word = 32-bits)
- size = (bcr >> 16) * (bcr & 0xffff);
- GPU_readDataMem(ptr, size);
- psxCpu->Clear(madr, size);
+ words = (bcr >> 16) * (bcr & 0xffff);
+ GPU_readDataMem(ptr, words);
+ psxCpu->Clear(madr, words);
+
+ HW_DMA2_MADR = SWAPu32(madr + words * 4);
// already 32-bit word size ((size * 4) / 4)
- GPUDMA_INT(size / 4);
+ GPUDMA_INT(words / 4);
return;
case 0x01000201: // mem2vram
break;
}
// BA blocks * BS words (word = 32-bits)
- size = (bcr >> 16) * (bcr & 0xffff);
- GPU_writeDataMem(ptr, size);
+ words = (bcr >> 16) * (bcr & 0xffff);
+ GPU_writeDataMem(ptr, words);
+
+ HW_DMA2_MADR = SWAPu32(madr + words * 4);
// already 32-bit word size ((size * 4) / 4)
- GPUDMA_INT(size / 4);
+ GPUDMA_INT(words / 4);
return;
case 0x01000401: // dma chain
size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff);
if ((int)size <= 0)
size = gpuDmaChainSize(madr);
- HW_GPU_STATUS &= ~PSXGPU_nBUSY;
-
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
+
+ // we don't emulate progress, just busy flag and end irq,
+ // so pretend we're already at the last block
+ HW_DMA2_MADR = SWAPu32(0xffffff);
+
// Tekken 3 = use 1.0 only (not 1.5x)
// Einhander = parse linked list in pieces (todo)
HW_DMA2_CHCR &= SWAP32(~0x01000000);
DMA_INTERRUPT(2);
}
- HW_GPU_STATUS |= PSXGPU_nBUSY; // GPU no longer busy
+ HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
}
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
- u32 size;
+ u32 words;
u32 *mem = (u32 *)PSXM(madr);
#ifdef PSXDMA_LOG
}
// already 32-bit size
- size = bcr;
+ words = bcr;
while (bcr--) {
*mem-- = SWAP32((madr - 4) & 0xffffff);
madr -= 4;
}
- mem++; *mem = 0xffffff;
+ *++mem = SWAP32(0xffffff);
- GPUOTCDMA_INT(size);
+ //GPUOTCDMA_INT(size);
+ // halted
+ psxRegs.cycle += words;
+ GPUOTCDMA_INT(16);
return;
}
#ifdef PSXDMA_LOG