#include "psxhw.h"
#include "mdec.h"
#include "cdrom.h"
+#include "gpu.h"
-void psxHwReset() {
- if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
- if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
+//#undef PSXHW_LOG
+//#define PSXHW_LOG printf
+void psxHwReset() {
memset(psxH, 0, 0x10000);
mdecInit(); // initialize mdec decoder
cdrReset();
psxRcntInit();
+ HW_GPU_STATUS = SWAP32(0x14802000);
}
u8 psxHwRead8(u32 add) {
unsigned char hard;
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040: hard = sioRead8();break; \r
#ifdef ENABLE_SIO1API
case 0x1f801050: hard = SIO1_readData8(); break;\r
u16 psxHwRead16(u32 add) {
unsigned short hard;
- switch (add) {
+ switch (add & 0x1fffffff) {
#ifdef PSXHW_LOG
case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
return psxHu16(0x1070);
return hard;
case 0x1f80105e:
hard = SIO1_readBaud16();
- return hard;\r
+ return hard;
+#else
+ /* Fixes Armored Core misdetecting the Link cable being detected.
+ * We want to turn that thing off and force it to do local multiplayer instead.
+ * Thanks Sony for the fix, they fixed it in their PS Classic fork.
+ */
+ case 0x1f801054:
+ return 0x80;\r
#endif
case 0x1f801100:
hard = psxRcntRcount(0);
//case 0x1f802030: hard = //int_2000????
//case 0x1f802040: hard =//dip switches...??
+ case 0x1f801800:
+ case 0x1f801802:
+ log_unhandled("cdrom r16 %x\n", add);
+ // falthrough
default:
if (add >= 0x1f801c00 && add < 0x1f801e00) {
hard = SPU_readRegister(add);
u32 psxHwRead32(u32 add) {
u32 hard;
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
hard = sioRead8();
hard |= sioRead8() << 8;
#endif
return hard;
case 0x1f801814:
- hard = GPU_readStatus();
+ gpuSyncPluginSR();
+ hard = SWAP32(HW_GPU_STATUS);
+ if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
#endif
#endif
return hard;
+ case 0x1f801800:
+ log_unhandled("cdrom r32 %x\n", add);
+ // falthrough
default:
hard = psxHu32(add);
#ifdef PSXHW_LOG
}
void psxHwWrite8(u32 add, u8 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040: sioWrite8(value); break;\r
#ifdef ENABLE_SIO1API
case 0x1f801050: SIO1_writeData8(value); break;\r
}
void psxHwWrite16(u32 add, u16 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)(value>>8));
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 16bit write %x\n", value);
#endif
- if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
- if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
- psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
+ psxHu16ref(0x1070) &= SWAPu16(value);
return;
case 0x1f801074:
PSXHW_LOG("IMASK 16bit write %x\n", value);
#endif
psxHu16ref(0x1074) = SWAPu16(value);
+ if (psxHu16ref(0x1070) & SWAPu16(value))
+ new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;
case 0x1f801100:
default:
if (add>=0x1f801c00 && add<0x1f801e00) {
- SPU_writeRegister(add, value);
+ SPU_writeRegister(add, value, psxRegs.cycle);
return;
}
}
#define DmaExec(n) { \
+ if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
+ log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
HW_DMA##n##_CHCR = SWAPu32(value); \
\
if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
}
void psxHwWrite32(u32 add, u32 value) {
- switch (add) {
+ switch (add & 0x1fffffff) {
case 0x1f801040:
sioWrite8((unsigned char)value);
sioWrite8((unsigned char)((value&0xff) >> 8));
#ifdef PSXHW_LOG
PSXHW_LOG("IREG 32bit write %x\n", value);
#endif
- if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
- if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
- psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
+ psxHu32ref(0x1070) &= SWAPu32(value);
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("IMASK 32bit write %x\n", value);
#endif
psxHu32ref(0x1074) = SWAPu32(value);
+ if (psxHu32ref(0x1070) & SWAPu32(value))
+ new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
return;
#ifdef PSXHW_LOG
PSXHW_LOG("DMA ICR 32bit write %x\n", value);
#endif
{
- u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
- HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp);
+ u32 tmp = value & 0x00ff803f;
+ tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
+ if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
+ || tmp & HW_DMA_ICR_BUS_ERROR) {
+ if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
+ psxHu32ref(0x1070) |= SWAP32(8);
+ tmp |= HW_DMA_ICR_IRQ_SENT;
+ }
+ HW_DMA_ICR = SWAPu32(tmp);
return;
}
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
#endif
- GPU_writeStatus(value); return;
+ GPU_writeStatus(value);
+ gpuSyncPluginSR();
+ return;
case 0x1f801820:
mdecWrite0(value); break;
psxRcntWtarget(2, value & 0xffff); return;
default:
+ // Dukes of Hazard 2 - car engine noise
+ if (add>=0x1f801c00 && add<0x1f801e00) {
+ SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
+ SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
+ return;
+ }
+
psxHu32ref(add) = SWAPu32(value);
#ifdef PSXHW_LOG
PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
#endif
}
-int psxHwFreeze(gzFile f, int Mode) {
+int psxHwFreeze(void *f, int Mode) {
return 0;
}