#include "psxhw.h"
#include "mdec.h"
#include "cdrom.h"
+#include "gpu.h"
+
+//#undef PSXHW_LOG
+//#define PSXHW_LOG printf
void psxHwReset() {
if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
mdecInit(); // initialize mdec decoder
cdrReset();
psxRcntInit();
+ HW_GPU_STATUS = 0x14802000;
}
u8 psxHwRead8(u32 add) {
#endif
return hard;
case 0x1f801814:
- hard = GPU_readStatus();
+ gpuSyncPluginSR();
+ hard = HW_GPU_STATUS;
+ if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+ hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
#endif
#endif
if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
- psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
+ psxHu16ref(0x1070) &= SWAPu16(value);
return;
case 0x1f801074:
#endif
if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
- psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
+ psxHu32ref(0x1070) &= SWAPu32(value);
return;
case 0x1f801074:
#ifdef PSXHW_LOG
PSXHW_LOG("DMA ICR 32bit write %x\n", value);
#endif
{
- u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
- HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp);
+ u32 tmp = value & 0x00ff803f;
+ tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
+ if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
+ || tmp & HW_DMA_ICR_BUS_ERROR) {
+ if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
+ psxHu32ref(0x1070) |= SWAP32(8);
+ tmp |= HW_DMA_ICR_IRQ_SENT;
+ }
+ HW_DMA_ICR = SWAPu32(tmp);
return;
}
#ifdef PSXHW_LOG
PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
#endif
- GPU_writeStatus(value); return;
+ GPU_writeStatus(value);
+ gpuSyncPluginSR();
+ return;
case 0x1f801820:
mdecWrite0(value); break;
#endif
}
-int psxHwFreeze(gzFile f, int Mode) {
+int psxHwFreeze(void *f, int Mode) {
return 0;
}