PSXINT_GPUOTCDMA,
PSXINT_CDRDMA,
PSXINT_NEWDRC_CHECK,
- DUMMY2,
+ PSXINT_RCNT,
PSXINT_CDRLID,
+ PSXINT_CDRPLAY,
+ PSXINT_SPU_UPDATE,
PSXINT_COUNT
};
+typedef struct psxCP2Regs {
+ psxCP2Data CP2D; /* Cop2 data registers */
+ psxCP2Ctrl CP2C; /* Cop2 control registers */
+} psxCP2Regs;
+
typedef struct {
psxGPRRegs GPR; /* General Purpose Registers */
psxCP0Regs CP0; /* Coprocessor0 Registers */
- psxCP2Data CP2D; /* Cop2 data registers */
- psxCP2Ctrl CP2C; /* Cop2 control registers */
+ union {
+ struct {
+ psxCP2Data CP2D; /* Cop2 data registers */
+ psxCP2Ctrl CP2C; /* Cop2 control registers */
+ };
+ psxCP2Regs CP2;
+ };
u32 pc; /* Program counter */
u32 code; /* The instruction */
u32 cycle;
extern u32 event_cycles[PSXINT_COUNT];
extern u32 next_interupt;
-void new_dyna_save(void);
-void new_dyna_restore(void);
+void new_dyna_before_save(void);
+void new_dyna_after_save(void);
+void new_dyna_freeze(void *f, int mode);
#define new_dyna_set_event(e, c) { \
s32 c_ = c; \