p32x_pwm_ctl_changed();
p32x_timers_recalc();
+ Pico32x.sh2_regs[0] = P32XS2_ADEN;
+ if (Pico.m.ncart_in)
+ Pico32x.sh2_regs[0] |= P32XS_nCART;
+
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
- Pico32x.sh2_regs[0] = P32XS2_ADEN;
}
void PicoUnload32x(void)
void PicoReset32x(void)
{
if (PicoAHW & PAHW_32X) {
- msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
oldest, event_time_next);
}
-static inline void run_sh2(SH2 *sh2, int m68k_cycles)
+static INLINE void run_sh2(SH2 *sh2, int m68k_cycles)
{
int cycles, done;
elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
sh2->m68krcycles_done, cycles, sh2->pc);
- done = sh2_execute(sh2, cycles);
+ done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
sh2->state &= ~SH2_STATE_RUN;
}
#define CPUS_RUN(m68k_cycles) do { \
- SekRunM68k(m68k_cycles); \
+ if (PicoAHW & PAHW_MCD) \
+ pcd_run_cpus(m68k_cycles); \
+ else \
+ SekRunM68k(m68k_cycles); \
+ \
if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
&& !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
PicoSyncZ80(SekCyclesDone()); \
} while (0)
#define PICO_32X
+#define PICO_CD
#include "../pico_cmn.c"
void PicoFrame32x(void)
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
+ if (PicoAHW & PAHW_MCD)
+ pcd_prepare_frame();
+
PicoFrameStart();
PicoFrameHints();
sh2_drc_frame();