/*
- * SH2 addr lines:
- * iii. .cc. ..xx * // Internal, Cs, x
+ * PicoDrive
+ * (C) notaz, 2009,2010,2013
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
*
* Register map:
* a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
* a1511e ? ? 401e
* a15120 (16 bytes comm) 2020
* a15130 (PWM) 2030
+ *
+ * SH2 addr lines:
+ * iii. .cc. ..xx * // Internal, Cs, x
+ *
+ * sh2 map, wait/bus cycles (from docs):
+ * r w
+ * rom 0000000-0003fff 1 -
+ * sys reg 0004000-00040ff 1 1
+ * vdp reg 0004100-00041ff 5 5
+ * vdp pal 0004200-00043ff 5 5
+ * rom 2000000-23fffff 6-15
+ * dram/fb 4000000-401ffff 5-12 1-3
+ * fb ovr 4020000-403ffff
+ * sdram 6000000-603ffff 12 2 (cycles)
+ * d.a. c0000000-?
*/
#include "../pico_int.h"
#include "../memory.h"
-#ifdef DRC_SH2
#include "../../cpu/sh2/compiler.h"
-#endif
-
-#if 0
-#undef ash2_end_run
-#undef SekEndRun
-#define ash2_end_run(x)
-#define SekEndRun(x)
-#endif
static const char str_mars[] = "MARS";
static void bank_switch(int b);
// poll detection
-#define POLL_THRESHOLD 6
+#define POLL_THRESHOLD 3
-struct poll_det {
- u32 addr, cycles, cyc_max;
- int cnt, flag;
-};
-static struct poll_det m68k_poll, sh2_poll[2];
+static struct {
+ u32 addr, cycles;
+ int cnt;
+} m68k_poll;
-static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
+static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
{
- int ret = 0, flag = pd->flag;
-
- if (is_vdp)
- flag <<= 3;
-
- if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
- pd->cnt++;
- if (pd->cnt > POLL_THRESHOLD) {
- if (!(Pico32x.emu_flags & flag)) {
- elprintf(EL_32X, "%s poll addr %08x, cyc %u",
- flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
- (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
+ int ret = 0;
+
+ if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
+ && cycles - m68k_poll.cycles <= 64)
+ {
+ if (m68k_poll.cnt++ > POLL_THRESHOLD) {
+ if (!(Pico32x.emu_flags & flags)) {
+ elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
+ a, cycles - m68k_poll.cycles);
ret = 1;
}
- Pico32x.emu_flags |= flag;
+ Pico32x.emu_flags |= flags;
}
}
else {
- pd->cnt = 0;
- pd->addr = a;
+ m68k_poll.cnt = 0;
+ m68k_poll.addr = a;
}
- pd->cycles = cycles;
+ m68k_poll.cycles = cycles;
return ret;
}
-static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
+void p32x_m68k_poll_event(u32 flags)
+{
+ if (Pico32x.emu_flags & flags) {
+ elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
+ Pico32x.emu_flags & ~flags);
+ Pico32x.emu_flags &= ~flags;
+ SekSetStop(0);
+ }
+ m68k_poll.addr = m68k_poll.cnt = 0;
+}
+
+static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
{
- int ret = 0, flag = pd->flag;
- if (is_vdp)
- flag <<= 3; // VDP only
+ int cycles_left = sh2_cycles_left(sh2);
+
+ if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
+ if (sh2->poll_cnt++ > 3) {
+ if (!(sh2->state & flags))
+ elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
+ sh2->state, sh2->state | flags);
+
+ sh2->state |= flags;
+ sh2_end_run(sh2, 1);
+ pevt_log_sh2(sh2, EVT_POLL_START);
+ return;
+ }
+ }
else
- flag |= flag << 3; // both
- if (Pico32x.emu_flags & flag) {
- elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
- ret = 1;
+ sh2->poll_cnt = 0;
+ sh2->poll_addr = a;
+ sh2->poll_cycles = cycles_left;
+}
+
+void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
+{
+ if (sh2->state & flags) {
+ elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
+ sh2->state, sh2->state & ~flags);
+
+ if (sh2->m68krcycles_done < m68k_cycles)
+ sh2->m68krcycles_done = m68k_cycles;
+
+ pevt_log_sh2_o(sh2, EVT_POLL_END);
}
- Pico32x.emu_flags &= ~flag;
- pd->addr = pd->cnt = 0;
- return ret;
+
+ sh2->state &= ~flags;
+ sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
}
-void p32x_poll_event(int cpu_mask, int is_vdp)
+static void sh2s_sync_on_read(SH2 *sh2)
{
- if (cpu_mask & 1)
- p32x_poll_undetect(&sh2_poll[0], is_vdp);
- if (cpu_mask & 2)
- p32x_poll_undetect(&sh2_poll[1], is_vdp);
+ int cycles;
+ if (sh2->poll_cnt != 0)
+ return;
+
+ cycles = sh2_cycles_done(sh2);
+ if (cycles > 600)
+ p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
}
// SH2 faking
//#define FAKE_SH2
-int p32x_csum_faked;
#ifdef FAKE_SH2
+static int p32x_csum_faked;
static const u16 comm_fakevals[] = {
0x4d5f, 0x4f4b, // M_OK
0x535f, 0x4f4b, // S_OK
elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
// HACK: assume bus is busy and SH2 is halted
- // XXX: use different mechanism for this, not poll det
- Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
+ msh2.state |= SH2_STATE_SLEEP;
for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
if (dmac0->tcr0 == 0) {
dmac0->chcr0 |= 2; // DMA has ended normally
- p32x_poll_undetect(&sh2_poll[0], 0);
+ p32x_sh2_poll_event(&sh2s[0], SH2_STATE_SLEEP, SekCyclesDoneT());
}
}
{
a &= 0x3e;
- if (a == 2) // INTM, INTS
- return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
#if 0
if ((a & 0x30) == 0x20)
return sh2_comm_faker(a);
#else
if ((a & 0x30) == 0x20) {
- // evil X-Men proto polls in a dbra loop and expects it to expire..
static u32 dr2 = 0;
+ unsigned int cycles = SekCyclesDoneT();
+ int comreg = 1 << (a & 0x0f) / 2;
+
+ // evil X-Men proto polls in a dbra loop and expects it to expire..
if (SekDar(2) != dr2)
m68k_poll.cnt = 0;
dr2 = SekDar(2);
- if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
+ if (cycles - msh2.m68krcycles_done > 500)
+ p32x_sync_sh2s(cycles);
+ if (Pico32x.comm_dirty_sh2 & comreg)
+ Pico32x.comm_dirty_sh2 &= ~comreg;
+ else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
SekSetStop(1);
SekEndTimeslice(16);
}
dr2 = SekDar(2);
+ goto out;
}
#endif
+ if (a == 2) { // INTM, INTS
+ unsigned int cycles = SekCyclesDoneT();
+ if (cycles - msh2.m68krcycles_done > 64)
+ p32x_sync_sh2s(cycles);
+ return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
+ }
+
if ((a & 0x30) == 0x30)
return p32x_pwm_read16(a);
+out:
return Pico32x.regs[a / 2];
}
return;
case 3: // irq ctl
if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[0] |= P32XI_CMD;
- p32x_update_irls();
- SekEndRun(16);
+ p32x_update_irls(NULL);
}
if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[1] |= P32XI_CMD;
- p32x_update_irls();
- SekEndRun(16);
+ p32x_update_irls(NULL);
}
return;
case 5: // bank
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)r;
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r8[a ^ 1] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r8[a ^ 1] = d;
- p32x_poll_undetect(&sh2_poll[0], 0);
- p32x_poll_undetect(&sh2_poll[1], 0);
- // if some SH2 is busy waiting, it needs to see the result ASAP
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
+ p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
}
case 0x12: // FIFO reg
if (!(r[6 / 2] & P32XS_68S)) {
elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
- return;
+ return;
}
if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
return;
}
// comm port
- else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
+ else if ((a & 0x30) == 0x20) {
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r[a / 2] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r[a / 2] = d;
- p32x_poll_undetect(&sh2_poll[0], 0);
- p32x_poll_undetect(&sh2_poll[1], 0);
- // same as for w8
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
+ p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
// PWM
u16 *r = Pico32x.vdp_regs;
a &= 0x0f;
- // for FEN checks between writes
- sh2_poll[0].cnt = 0;
-
// TODO: verify what's writeable
switch (a) {
case 0x01:
Pico32x.dirty_pal = 1;
r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
break;
+ case 0x03: // shift (for pp mode)
+ r[2 / 2] = d & 1;
+ break;
case 0x05: // fill len
r[4 / 2] = d & 0xff;
break;
Pico32x.pending_fb = d;
// if we are blanking and FS bit is changing
if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
- r[0x0a/2] ^= 1;
- Pico32xSwapDRAM(d ^ 1);
+ r[0x0a/2] ^= P32XV_FS;
+ Pico32xSwapDRAM(d ^ 1);
elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
}
break;
}
}
-static void p32x_vdp_write16(u32 a, u32 d)
+static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
{
a &= 0x0e;
if (a == 6) { // fill start
if (a == 8) { // fill data
u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
int len = Pico32x.vdp_regs[4 / 2] + 1;
+ int len1 = len;
a = Pico32x.vdp_regs[6 / 2];
- while (len--) {
+ while (len1--) {
dram[a] = d;
a = (a & 0xff00) | ((a + 1) & 0xff);
}
- Pico32x.vdp_regs[6 / 2] = a;
- Pico32x.vdp_regs[8 / 2] = d;
+ Pico32x.vdp_regs[0x06 / 2] = a;
+ Pico32x.vdp_regs[0x08 / 2] = d;
+ if (sh2 != NULL && len > 4) {
+ Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
+ // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
+ p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
+ }
return;
}
case 0x00: // adapter/irq ctl
return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
case 0x04: // H count (often as comm too)
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
- ash2_end_run(8);
+ sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
+ sh2s_sync_on_read(&sh2s[cpuid]);
return Pico32x.sh2_regs[4 / 2];
case 0x10: // DREQ len
return r[a / 2];
return r[a / 2];
// comm port
if ((a & 0x30) == 0x20) {
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
- ash2_end_run(8);
+ int comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ Pico32x.comm_dirty_68k &= ~comreg;
+ else
+ sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
+ sh2s_sync_on_read(&sh2s[cpuid]);
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
- sh2_poll[cpuid].cnt = 0;
return p32x_pwm_read16(a);
}
static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
{
a &= 0xff;
+
+ sh2s[cpuid].poll_addr = 0;
+
switch (a) {
case 0: // FM
Pico32x.regs[0] &= ~P32XS_FM;
Pico32x.regs[0] |= (d << 8) & P32XS_FM;
return;
- case 1: //
+ case 1: // HEN/irq masks
+ if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
+ elprintf(EL_ANOMALY|EL_32X, "HEN");
Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
- p32x_update_irls();
+ if (d & 1)
+ p32x_pwm_schedule_sh2(&sh2s[cpuid]);
+ p32x_update_irls(&sh2s[cpuid]);
return;
case 5: // H count
- Pico32x.sh2_regs[4 / 2] = d & 0xff;
- p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ d &= 0xff;
+ if (Pico32x.sh2_regs[4 / 2] != d) {
+ Pico32x.sh2_regs[4 / 2] = d;
+ p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(&sh2s[cpuid]));
+ sh2_end_run(&sh2s[cpuid], 4);
+ }
return;
}
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)Pico32x.regs;
+ int comreg;
+ if (r8[a ^ 1] == d)
+ return;
+
r8[a ^ 1] = d;
- if (p32x_poll_undetect(&m68k_poll, 0))
- SekSetStop(0);
- p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ p32x_m68k_poll_event(P32XF_68KCPOLL);
+ p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(&sh2s[cpuid]));
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
{
a &= 0xfe;
+ sh2s[cpuid].poll_addr = 0;
+
// comm
- if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
+ if ((a & 0x30) == 0x20) {
+ int comreg;
+ if (Pico32x.regs[a / 2] == d)
+ return;
+
Pico32x.regs[a / 2] = d;
- if (p32x_poll_undetect(&m68k_poll, 0))
- SekSetStop(0);
- p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ p32x_m68k_poll_event(P32XF_68KCPOLL);
+ p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(&sh2s[cpuid]));
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_timers_do(0);
+ if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
+ p32x_pwm_schedule_sh2(&sh2s[cpuid]);
goto irls;
}
return;
irls:
- p32x_update_irls();
+ p32x_update_irls(&sh2s[cpuid]);
}
// ------------------------------------------------------------------
return d;
}
-static void sh2_peripheral_write8(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
{
u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
int vector = PREG8(oregs, 0x63) & 0x7f;
elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
sh2_internal_irq(&sh2s[id ^ 1], level, vector);
+ return 1;
}
}
+ return 0;
}
-static void sh2_peripheral_write16(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
{
u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
}
if ((d & 0xff00) == 0x5a00) // WTCNT
PREG8(r, 0x81) = d;
- return;
+ return 0;
}
r[(a / 2) ^ 1] = d;
+ return 0;
}
static void sh2_peripheral_write32(u32 a, u32 d, int id)
dmac0->tcr0 &= 0xffffff;
// HACK: assume 68k starts writing soon and end the timeslice
- ash2_end_run(16);
+ sh2_end_run(&sh2s[id], 16);
// DREQ is only sent after first 4 words are written.
// we do multiple of 4 words to avoid messing up alignment
return;
}
- if ((a & 0xfff0) == 0x5180) { // a15180
- p32x_vdp_write8(a, d);
- return;
- }
+ if (!(Pico32x.regs[0] & P32XS_FM)) {
+ if ((a & 0xfff0) == 0x5180) { // a15180
+ p32x_vdp_write8(a, d);
+ return;
+ }
- // TODO: verify
- if ((a & 0xfe00) == 0x5200) { // a15200
- elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
- ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
- Pico32x.dirty_pal = 1;
- return;
+ // TODO: verify
+ if ((a & 0xfe00) == 0x5200) { // a15200
+ elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
+ ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
+ Pico32x.dirty_pal = 1;
+ return;
+ }
}
elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
return;
}
- if ((a & 0xfff0) == 0x5180) { // a15180
- p32x_vdp_write16(a, d);
- return;
- }
+ if (!(Pico32x.regs[0] & P32XS_FM)) {
+ if ((a & 0xfff0) == 0x5180) { // a15180
+ p32x_vdp_write16(a, d, NULL); // FIXME?
+ return;
+ }
- if ((a & 0xfe00) == 0x5200) { // a15200
- Pico32xMem->pal[(a & 0x1ff) / 2] = d;
- Pico32x.dirty_pal = 1;
- return;
+ if ((a & 0xfe00) == 0x5200) { // a15200
+ Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+ Pico32x.dirty_pal = 1;
+ return;
+ }
}
elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
#ifdef EMU_F68K
// setup FAME fetchmap
for (rs = 0x90; rs < 0xa0; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
#endif
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
- ash2_end_run(8);
+ sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
goto out_16to8;
}
if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
return Pico32xMem->sh2_rom_s[a ^ 1];
- if ((a & 0x3ff00) == 0x4200) {
+ if ((a & 0x3fe00) == 0x4200) {
d = Pico32xMem->pal[(a & 0x1ff) / 2];
goto out_16to8;
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
- ash2_end_run(8);
+ sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
goto out;
}
if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
return *(u16 *)(Pico32xMem->sh2_rom_s + a);
- if ((a & 0x3ff00) == 0x4200) {
+ if ((a & 0x3fe00) == 0x4200) {
d = Pico32xMem->pal[(a & 0x1ff) / 2];
goto out;
}
return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
}
+static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+{
+ return 0;
+}
+
// write8
-static void sh2_write8_unmapped(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
{
elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+ return 0;
}
-static void sh2_write8_cs0(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
{
elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
- if ((a & 0x3ff00) == 0x4100) {
- p32x_vdp_write8(a, d);
- return;
+ if (Pico32x.regs[0] & P32XS_FM) {
+ if ((a & 0x3ff00) == 0x4100) {
+ sh2s[id].poll_addr = 0;
+ p32x_vdp_write8(a, d);
+ return 0;
+ }
}
if ((a & 0x3ff00) == 0x4000) {
p32x_sh2reg_write8(a, d, id);
- return;
+ return 1;
}
- sh2_write8_unmapped(a, d, id);
+ return sh2_write8_unmapped(a, d, id);
}
+/* quirk: in both normal and overwrite areas only nonzero values go through */
#define sh2_write8_dramN(n) \
- if (!(a & 0x20000) || d) { \
+ if ((d & 0xff) != 0) { \
u8 *dram = (u8 *)Pico32xMem->dram[n]; \
dram[(a & 0x1ffff) ^ 1] = d; \
- }
+ } \
+ return 0;
-static void sh2_write8_dram0(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
{
sh2_write8_dramN(0);
}
-static void sh2_write8_dram1(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
{
sh2_write8_dramN(1);
}
-static void sh2_write8_sdram(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
sh2_drc_wcheck_ram(a, t, id);
#endif
Pico32xMem->sdram[a1 ^ 1] = d;
+ return 0;
}
-static void sh2_write8_da(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
sh2_drc_wcheck_da(a, t, id);
#endif
Pico32xMem->data_array[id][a1 ^ 1] = d;
+ return 0;
}
// write16
-static void sh2_write16_unmapped(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
{
elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+ return 0;
}
-static void sh2_write16_cs0(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
{
if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
- if ((a & 0x3ff00) == 0x4100) {
- sh2_poll[id].cnt = 0; // for poll before VDP accesses
- p32x_vdp_write16(a, d);
- return;
- }
+ if (Pico32x.regs[0] & P32XS_FM) {
+ if ((a & 0x3ff00) == 0x4100) {
+ sh2s[id].poll_addr = 0;
+ p32x_vdp_write16(a, d, &sh2s[id]);
+ return 0;
+ }
- if ((a & 0x3fe00) == 0x4200) {
- Pico32xMem->pal[(a & 0x1ff) / 2] = d;
- Pico32x.dirty_pal = 1;
- return;
+ if ((a & 0x3fe00) == 0x4200) {
+ Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+ Pico32x.dirty_pal = 1;
+ return 0;
+ }
}
if ((a & 0x3ff00) == 0x4000) {
p32x_sh2reg_write16(a, d, id);
- return;
+ return 1;
}
- sh2_write16_unmapped(a, d, id);
+ return sh2_write16_unmapped(a, d, id);
}
#define sh2_write16_dramN(n) \
u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
if (!(a & 0x20000)) { \
*pd = d; \
- return; \
+ return 0; \
} \
/* overwrite */ \
if (!(d & 0xff00)) d |= *pd & 0xff00; \
if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
- *pd = d
+ *pd = d; \
+ return 0
-static void sh2_write16_dram0(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
{
sh2_write16_dramN(0);
}
-static void sh2_write16_dram1(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
{
sh2_write16_dramN(1);
}
-static void sh2_write16_sdram(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
sh2_drc_wcheck_ram(a, t, id);
#endif
((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
+ return 0;
}
-static void sh2_write16_da(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
sh2_drc_wcheck_da(a, t, id);
#endif
((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
+ return 0;
}
-typedef struct {
- uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
- u32 mask;
-} sh2_memmap;
+typedef u32 (sh2_read_handler)(u32 a, int id);
+typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
-typedef u32 (sh2_read_handler)(u32 a, int id);
-typedef void (sh2_write_handler)(u32 a, u32 d, int id);
+#define SH2MAP_ADDR2OFFS_R(a) \
+ ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
-#define SH2MAP_ADDR2OFFS(a) \
- (((a >> 25) & 3) | ((a >> 27) & 0x1c))
+#define SH2MAP_ADDR2OFFS_W(a) \
+ ((u32)(a) >> SH2_WRITE_SHIFT)
u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
{
const sh2_memmap *sh2_map = sh2->read8_map;
uptr p;
- sh2_map += SH2MAP_ADDR2OFFS(a);
+ sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
- if (p & (1 << 31))
+ if (map_flag_set(p))
return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
else
return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
const sh2_memmap *sh2_map = sh2->read16_map;
uptr p;
- sh2_map += SH2MAP_ADDR2OFFS(a);
+ sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
- if (p & (1 << 31))
+ if (map_flag_set(p))
return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
else
return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
u32 offs;
uptr p;
- offs = SH2MAP_ADDR2OFFS(a);
+ offs = SH2MAP_ADDR2OFFS_R(a);
sh2_map += offs;
p = sh2_map->addr;
- if (!(p & (1 << 31))) {
+ if (!map_flag_set(p)) {
// XXX: maybe 32bit access instead with ror?
u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
return (pd[0] << 16) | pd[1];
return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
}
-void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+// return nonzero if write potentially causes an interrupt (used by drc)
+int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write8_tab;
sh2_write_handler *wh;
- wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
- wh(a, d, sh2->is_slave);
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+ return wh(a, d, sh2->is_slave);
}
-void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write16_tab;
sh2_write_handler *wh;
- wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
- wh(a, d, sh2->is_slave);
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+ return wh(a, d, sh2->is_slave);
}
-void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write16_tab;
sh2_write_handler *handler;
u32 offs;
- offs = SH2MAP_ADDR2OFFS(a);
+ offs = SH2MAP_ADDR2OFFS_W(a);
- if (offs == 0x1f) {
+ if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
sh2_peripheral_write32(a, d, sh2->is_slave);
- return;
+ return 0;
}
handler = sh2_wmap[offs];
handler(a, d >> 16, sh2->is_slave);
handler(a + 2, d, sh2->is_slave);
+ return 0;
}
// -----------------------------------------------------------------
// M68K ROM
if (p32x_bios_g != NULL) {
elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
- Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
+ Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
}
else {
// generate 68k ROM
#endif
}
// fill remaining m68k_rom page with game ROM
- memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
+ memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
+ Pico.rom + sizeof(Pico32xMem->m68k_rom),
+ sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
// MSH2
if (p32x_bios_m != NULL) {
}
#define MAP_MEMORY(m) ((uptr)(m) >> 1)
-#define MAP_HANDLER(h) (((uptr)(h) >> 1) | (1 << 31))
+#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
// for writes we are using handlers only
-static void *sh2_write8_map[0x20], *sh2_write16_map[0x20];
+static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
void Pico32xSwapDRAM(int b)
{
sh2_read8_map[2].addr = sh2_read8_map[6].addr =
sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
- sh2_write8_map[2] = sh2_write8_map[6] = b ? sh2_write8_dram1 : sh2_write8_dram0;
- sh2_write16_map[2] = sh2_write16_map[6] = b ? sh2_write16_dram1 : sh2_write16_dram0;
+ sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
+ sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
}
void PicoMemSetup32x(void)
unsigned int rs;
int i;
- Pico32xMem = calloc(1, sizeof(*Pico32xMem));
+ Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
if (Pico32xMem == NULL) {
elprintf(EL_STATUS, "OOM");
return;
// m68k_map_unmap(0x000000, 0x3fffff);
// MD ROM area
- rs = sizeof(Pico32xMem->m68k_rom);
- cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
- cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
+ rs = sizeof(Pico32xMem->m68k_rom_bank);
+ cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
+ cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
#ifdef EMU_F68K
// setup FAME fetchmap
- PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
+ PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
for (rs = 0x88; rs < 0x90; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
#endif
// 32X ROM (banked)
// SH2 maps: A31,A30,A29,CS1,CS0
// all unmapped by default
- for (i = 0; i < 0x20; i++) {
+ for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
sh2_write8_map[i] = sh2_write8_unmapped;
sh2_write16_map[i] = sh2_write16_unmapped;
}
+ // "purge area"
+ for (i = 0x40; i <= 0x5f; i++) {
+ sh2_write8_map[i >> 1] =
+ sh2_write16_map[i >> 1] = sh2_write_ignore;
+ }
+
// CS0
sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
- sh2_write8_map[0] = sh2_write8_map[4] = sh2_write8_cs0;
- sh2_write16_map[0] = sh2_write16_map[4] = sh2_write16_cs0;
+ sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
+ sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
// CS1 - ROM
sh2_read8_map[1].addr = sh2_read8_map[5].addr =
sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
// CS3 - SDRAM
sh2_read8_map[3].addr = sh2_read8_map[7].addr =
sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
- sh2_write8_map[3] = sh2_write8_map[7] = sh2_write8_sdram;
- sh2_write16_map[3] = sh2_write16_map[7] = sh2_write16_sdram;
+ sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
+ sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
sh2_read8_map[3].mask = sh2_read8_map[7].mask =
sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
// SH2 data array
sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
- sh2_write8_map[0x18] = sh2_write8_da;
- sh2_write16_map[0x18] = sh2_write16_da;
+ sh2_write8_map[0xc0/2] = sh2_write8_da;
+ sh2_write16_map[0xc0/2] = sh2_write16_da;
// SH2 IO
sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
- sh2_write8_map[0x1f] = sh2_peripheral_write8;
- sh2_write16_map[0x1f] = sh2_peripheral_write16;
+ sh2_write8_map[0xff/2] = sh2_peripheral_write8;
+ sh2_write16_map[0xff/2] = sh2_peripheral_write16;
// map DRAM area, both 68k and SH2
Pico32xSwapDRAM(1);
msh2.read8_map = ssh2.read8_map = sh2_read8_map;
msh2.read16_map = ssh2.read16_map = sh2_read16_map;
- msh2.write8_tab = ssh2.write8_tab = (const void **)sh2_write8_map;
- msh2.write16_tab = ssh2.write16_tab = (const void **)sh2_write16_map;
-
- // setup poll detector
- m68k_poll.flag = P32XF_68KPOLL;
- m68k_poll.cyc_max = 64;
- sh2_poll[0].flag = P32XF_MSH2POLL;
- sh2_poll[0].cyc_max = 21;
- sh2_poll[1].flag = P32XF_SSH2POLL;
- sh2_poll[1].cyc_max = 16;
+ msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
+ msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
+
+ sh2_drc_mem_setup(&msh2);
+ sh2_drc_mem_setup(&ssh2);
+}
+
+void Pico32xMemStateLoaded(void)
+{
+ bank_switch(Pico32x.regs[4 / 2]);
+ Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
+ memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
+ Pico32x.dirty_pal = 1;
+
+ Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
+ memset(&m68k_poll, 0, sizeof(m68k_poll));
+ msh2.state = 0;
+ msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
+ ssh2.state = 0;
+ ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
+
+ sh2_drc_flush_all();
}
-// vim:shiftwidth=2:expandtab
+// vim:shiftwidth=2:ts=2:expandtab