{
chan->chcr |= DMA_TE; // DMA has ended normally
- p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
+ p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
if (chan->chcr & DMA_IE)
dmac_te_irq(sh2, chan);
}
r[(a / 2) ^ 1] = d;
}
-void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
{
u32 *r = sh2->peri_regs;
u32 old;