{
chan->chcr |= DMA_TE; // DMA has ended normally
- p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
+ p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
if (chan->chcr & DMA_IE)
dmac_te_irq(sh2, chan);
}
return;
}
+ // DREQ1
+ if ((chan->dar & 0xc7fffff0) == 0x00004030)
+ return;
+
elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
"%08x->%08x, cnt %d, chcr %04x @%06x",
chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
r[(a / 2) ^ 1] = d;
}
-void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
{
u32 *r = sh2->peri_regs;
u32 old;
hit = 1;
}
- if (!hit)
- elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
+ // debug
+#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
+ {
+ static int miss_count;
+ if (!hit) {
+ if (++miss_count == 4)
+ elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
+ }
+ else
+ miss_count = 0;
+ }
+#endif
+ (void)hit;
}
// vim:shiftwidth=2:ts=2:expandtab