#define rdprintf(...)\r
//#define wrdprintf dprintf\r
#define wrdprintf(...)\r
+//#define r3printf elprintf\r
#define r3printf(...)\r
#endif\r
\r
goto end;\r
case 2:\r
d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
- // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)\r
- if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }\r
r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
goto end;\r
case 4:\r
case 1:\r
d &= 3;\r
if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset\r
- if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r
- if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r
+ if ( (Pico_mcd->m.busreq&1) != (d&1)) elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));\r
+ if ( (Pico_mcd->m.busreq&2) != (d&2)) elprintf(EL_INTSW, "m68k: s68k brq %i", (d&2)>>1);\r
if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {\r
SekResetS68k(); // S68k comes out of RESET or BRQ state\r
Pico_mcd->m.state_flags&=~1;\r
//if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r
//if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r
// ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r
- if (dold & 4) {\r
- d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
+ if (dold & 4) { // 1M mode\r
+ d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing\r
} else {\r
- //dold &= ~2; // ??\r
-#if 1\r
- if (d & (d ^ dold) & 2) { // DMNA is being set\r
- Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)\r
- d &= ~2;\r
- }\r
- else\r
- Pico_mcd->m.state_flags &= ~2;\r
-#else\r
- if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode\r
-#endif\r
+ if ((d ^ dold) & d & 2) { // DMNA is being set\r
+ dold &= ~1; // return word RAM to s68k\r
+ /* Silpheed hack: bset(w3), r3, btst, bne, r3 */\r
+ SekEndRun(20+16+10+12+16);\r
+ }\r
}\r
Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register\r
#ifdef USE_POLL_DETECT\r
wram_1M_to_2M(Pico_mcd->word_ram2M);\r
PicoMemResetCD(d);\r
}\r
- else\r
- d |= dold&1;\r
- if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
+ // s68k can only set RET, writing 0 has no effect\r
+ else if ((dold ^ d) & d & 1) { // RET being set\r
+ SekEndRunS68k(20+16+10+12+16); // see DMNA case\r
+ } else\r
+ d |= dold & 1;\r
+ if (d & 1)\r
+ d &= ~2; // DMNA clears\r
}\r
- Pico_mcd->m.state_flags &= ~2;\r
break;\r
}\r
case 4:\r