void m68k_comm_check(u32 a)\r
{\r
pcd_sync_s68k(SekCyclesDone(), 0);\r
+ if (a >= 0x0e && !Pico_mcd->m.need_sync) {\r
+ // there are cases when slave updates comm and only switches RAM\r
+ // over after that (mcd1b), so there must be a resync..\r
+ SekEndRun(64);\r
+ Pico_mcd->m.need_sync = 1;\r
+ }\r
if (SekNotPolling || a != Pico_mcd->m.m68k_poll_a) {\r
Pico_mcd->m.m68k_poll_a = a;\r
Pico_mcd->m.m68k_poll_cnt = 0;\r
//dprintf("s68k CDC reg addr: %x", d&0xf);\r
break;\r
case 7:\r
- cdc_reg_w(d);\r
+ cdc_reg_w(d & 0xff);\r
return;\r
case 0xa:\r
elprintf(EL_CDREGS, "s68k set CDC dma addr");\r