!!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
- sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count); MVP;
+ sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDoneT()); MVP;
+ sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
#if defined(EMU_C68K)
- sprintf(dstrp, "M68k: PC: %06x, st_flg: %x, cycles: %u\n", SekPc, PicoCpuCM68k.state_flags, SekCyclesDoneT()); MVP;
- sprintf(dstrp, "d0=%08x, a0=%08x, osp=%08x, irql=%i\n", PicoCpuCM68k.d[0], PicoCpuCM68k.a[0], PicoCpuCM68k.osp, PicoCpuCM68k.irq); MVP;
- sprintf(dstrp, "d1=%08x, a1=%08x, sr=%04x\n", PicoCpuCM68k.d[1], PicoCpuCM68k.a[1], CycloneGetSr(&PicoCpuCM68k)); dstrp+=strlen(dstrp); MVP;
- for(r=2; r < 8; r++) {
- sprintf(dstrp, "d%i=%08x, a%i=%08x\n", r, PicoCpuCM68k.d[r], r, PicoCpuCM68k.a[r]); MVP;
- }
-#elif defined(EMU_M68K)
- sprintf(dstrp, "M68k: PC: %06x, cycles: %u, irql: %i\n", SekPc, SekCyclesDoneT(), PicoCpuMM68k.int_level>>8); MVP;
-#elif defined(EMU_F68K)
- sprintf(dstrp, "M68k: PC: %06x, cycles: %u, irql: %i\n", SekPc, SekCyclesDoneT(), PicoCpuFM68k.interrupts[0]); MVP;
+ sprintf(dstrp - 1, ", st_flg: %x\n", PicoCpuCM68k.state_flags); MVP;
#endif
+ for (r = 0; r < 8; r++) {
+ sprintf(dstrp, "d%i=%08x, a%i=%08x\n", r, SekDar(r), r, SekDar(r+8)); MVP;
+ }
sprintf(dstrp, "z80Run: %i, z80_reset: %i, z80_bnk: %06x\n", Pico.m.z80Run, Pico.m.z80_reset, Pico.m.z80_bank68k<<15); MVP;
z80_debug(dstrp); MVP;
if (strlen(dstr) > sizeof(dstr))
return dstr;
}
+char *PDebug32x(void)
+{
+ char *dstrp = dstr;
+ unsigned short *r;
+ int i;
+
+ r = Pico32x.regs;
+ sprintf(dstrp, "regs:\n"); MVP;
+ for (i = 0; i < 0x40/2; i += 8) {
+ sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+ i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+ }
+ r = Pico32x.sh2_regs;
+ sprintf(dstrp, "SH: %04x %04x %04x IRQs: %02x eflags: %02x\n",
+ r[0], r[1], r[2], Pico32x.sh2irqs, Pico32x.emu_flags); MVP;
+
+ i = 0;
+ r = Pico32x.vdp_regs;
+ sprintf(dstrp, "VDP regs:\n"); MVP;
+ sprintf(dstrp, "%02x: %04x %04x %04x %04x %04x %04x %04x %04x\n",
+ i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
+
+ sprintf(dstrp, " mSH2 sSH2\n"); MVP;
+ sprintf(dstrp, "PC,SR %08x, %03x %08x, %03x\n", sh2_pc(0), sh2_sr(0), sh2_pc(1), sh2_sr(1)); MVP;
+ for (i = 0; i < 16/2; i++) {
+ sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
+ sh2_reg(0,i), sh2_reg(0,i+8), sh2_reg(1,i), sh2_reg(1,i+8)); MVP;
+ }
+ sprintf(dstrp, "gb,vb %08x,%08x %08x,%08x\n", sh2_gbr(0), sh2_vbr(0), sh2_gbr(1), sh2_vbr(1)); MVP;
+ sprintf(dstrp, "IRQs/mask: %02x/%02x %02x/%02x\n",
+ Pico32x.sh2irqi[0], Pico32x.sh2irq_mask[0], Pico32x.sh2irqi[1], Pico32x.sh2irq_mask[1]); MVP;
+
+ return dstr;
+}
+
char *PDebugSpriteList(void)
{
struct PicoVideo *pvid=&Pico.video;
dump_ram_noswab(Pico_mcd->pcm_ram,"dumps/pcm_ram.bin");
dump_ram_noswab(Pico_mcd->bram, "dumps/bram.bin");
}
+
+ if (PicoAHW & PAHW_32X)
+ {
+ dump_ram(Pico32xMem->sdram, "dumps/sdram.bin");
+ dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
+ dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
+ dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
+ dump_ram(Pico32xMem->data_array[0], "dumps/data_array0.bin");
+ dump_ram(Pico32xMem->data_array[1], "dumps/data_array1.bin");
+ }
}
void PDebugZ80Frame(void)
void PDebugCPUStep(void)
{
if (PicoAHW & PAHW_SMS)
- z80_run(1);
+ z80_run_nr(1);
else
SekStepM68k();
}