unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
\r
elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
- (d&2)>>1, d&1, SekCyclesDoneT() - last_write);\r
+ (d&2)>>1, d&1, SekCyclesDone() - last_write);\r
saddr &= 0x1fff;\r
\r
if(sreg & d & 2) {\r
{\r
// we are started and SCL went high - next cycle\r
scyc++; // pre-increment\r
- if(SRam.eeprom_type) {\r
+ if(Pico.sv.eeprom_type) {\r
// X24C02+\r
if((ssa&1) && scyc == 18) {\r
scyc = 9;\r
saddr++; // next address in read mode\r
- /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
+ /*if(Pico.sv.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
}\r
- else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
+ else if(Pico.sv.eeprom_type == 2 && scyc == 27) scyc = 18;\r
else if(scyc == 36) scyc = 27;\r
} else {\r
// X24C01\r
else if((sreg & 8) && (sreg & 2) && !(d&2))\r
{\r
// we are started and SCL went low (falling edge)\r
- if(SRam.eeprom_type) {\r
+ if(Pico.sv.eeprom_type) {\r
// X24C02+\r
if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
- else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {\r
+ else if( (Pico.sv.eeprom_type == 3 && scyc > 27) || (Pico.sv.eeprom_type == 2 && scyc > 18) ) {\r
if(!(ssa&1)) {\r
// data write\r
- unsigned char *pm=SRam.data+saddr;\r
+ unsigned char *pm=Pico.sv.data+saddr;\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 26 || scyc == 35) {\r
saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
}\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
} else if(scyc > 9) {\r
if(!(ssa&1)) {\r
// we latch another addr bit\r
saddr<<=1;\r
- if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ if(Pico.sv.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
saddr|=d&1;\r
if(scyc==17||scyc==26) {\r
elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
- if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
+ if(scyc==17&&Pico.sv.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
}\r
}\r
} else {\r
else if(scyc > 9) {\r
if(!(saddr&1)) {\r
// data write\r
- unsigned char *pm=SRam.data+(saddr>>1);\r
+ unsigned char *pm=Pico.sv.data+(saddr>>1);\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 17) {\r
saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented\r
elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
}\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
} else {\r
// we latch another addr bit\r
sreg &= ~0xc0;\r
\r
// SCL\r
- d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
+ d1 = (d >> Pico.sv.eeprom_bit_cl) & 1;\r
sreg |= d1 << 7;\r
\r
// SDA in\r
- d1 = (d >> SRam.eeprom_bit_in) & 1;\r
+ d1 = (d >> Pico.sv.eeprom_bit_in) & 1;\r
sreg |= d1 << 6;\r
\r
Pico.m.eeprom_status = (unsigned char) sreg;\r
void EEPROM_write16(unsigned int d)\r
{\r
// this diff must be at most 16 for NBA Jam to work\r
- if (SekCyclesDoneT() - last_write < 16) {\r
+ if (SekCyclesDone() - last_write < 16) {\r
// just update pending state\r
elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",\r
- SekCyclesDoneT() - last_write);\r
+ SekCyclesDone() - last_write);\r
EEPROM_upd_pending(d);\r
} else {\r
int srs = Pico.m.eeprom_status;\r
EEPROM_write_do(srs >> 6); // execute pending\r
EEPROM_upd_pending(d);\r
if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed\r
- last_write = SekCyclesDoneT();\r
+ last_write = SekCyclesDone();\r
}\r
}\r
\r
EEPROM_write_do(Pico.m.eeprom_status>>6);\r
\r
sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
- interval = SekCyclesDoneT() - last_write;\r
+ interval = SekCyclesDone() - last_write;\r
d = (sreg>>6)&1; // use SDA as "open bus"\r
\r
// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
} else if (scyc > 9 && scyc < 18) {\r
// started and first command word received\r
shift = 17-scyc;\r
- if (SRam.eeprom_type) {\r
+ if (Pico.sv.eeprom_type) {\r
// X24C02+\r
if (ssa&1) {\r
elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
- if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
- d = (SRam.data[saddr]>>shift)&1;\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr]);\r
+ d = (Pico.sv.data[saddr]>>shift)&1;\r
}\r
} else {\r
// X24C01\r
if (saddr&1) {\r
elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
- if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
- d = (SRam.data[saddr>>1]>>shift)&1;\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr>>1]);\r
+ d = (Pico.sv.data[saddr>>1]>>shift)&1;\r
}\r
}\r
}\r
\r
- return (d << SRam.eeprom_bit_out);\r
+ return (d << Pico.sv.eeprom_bit_out);\r
}\r
\r