\r
extern unsigned int lastSSRamWrite; // used by serial eeprom code\r
\r
-unsigned long m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
-unsigned long m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
-unsigned long m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
-unsigned long m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
+uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];\r
+uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];\r
+uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];\r
+uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
\r
-static void xmap_set(unsigned long *map, int shift, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,\r
+ const void *func_or_mh, int is_func)\r
{\r
- unsigned long addr = (unsigned long)func_or_mh;\r
+ uptr addr = (uptr)func_or_mh;\r
int mask = (1 << shift) - 1;\r
int i;\r
\r
for (i = start_addr >> shift; i <= end_addr >> shift; i++) {\r
map[i] = addr >> 1;\r
if (is_func)\r
- map[i] |= 1 << (sizeof(addr) * 8 - 1);\r
+ map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);\r
}\r
}\r
\r
-void z80_map_set(unsigned long *map, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+void z80_map_set(uptr *map, int start_addr, int end_addr,\r
+ const void *func_or_mh, int is_func)\r
{\r
xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
}\r
\r
-void cpu68k_map_set(unsigned long *map, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+void cpu68k_map_set(uptr *map, int start_addr, int end_addr,\r
+ const void *func_or_mh, int is_func)\r
{\r
xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
}\r
// more specialized/optimized function (does same as above)\r
void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)\r
{\r
- unsigned long *r8map, *r16map, *w8map, *w16map;\r
- unsigned long addr = (unsigned long)ptr;\r
+ uptr *r8map, *r16map, *w8map, *w16map;\r
+ uptr addr = (uptr)ptr;\r
int shift = M68K_MEM_SHIFT;\r
int i;\r
\r
\r
void m68k_map_unmap(int start_addr, int end_addr)\r
{\r
- unsigned long addr;\r
+ uptr addr;\r
int shift = M68K_MEM_SHIFT;\r
int i;\r
\r
- addr = (unsigned long)m68k_unmapped_read8;\r
+ addr = (uptr)m68k_unmapped_read8;\r
for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
m68k_read8_map[i] = (addr >> 1) | (1 << 31);\r
\r
- addr = (unsigned long)m68k_unmapped_read16;\r
+ addr = (uptr)m68k_unmapped_read16;\r
for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
m68k_read16_map[i] = (addr >> 1) | (1 << 31);\r
\r
- addr = (unsigned long)m68k_unmapped_write8;\r
+ addr = (uptr)m68k_unmapped_write8;\r
for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
m68k_write8_map[i] = (addr >> 1) | (1 << 31);\r
\r
- addr = (unsigned long)m68k_unmapped_write16;\r
+ addr = (uptr)m68k_unmapped_write16;\r
for (i = start_addr >> shift; i <= end_addr >> shift; i++)\r
m68k_write16_map[i] = (addr >> 1) | (1 << 31);\r
}\r
static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
static void z80_mem_setup(void);\r
\r
+#ifdef _ASM_MEMORY_C\r
+u32 PicoRead8_sram(u32 a);\r
+u32 PicoRead16_sram(u32 a);\r
+#endif\r
\r
#ifdef EMU_CORE_DEBUG\r
u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
#endif\r
\r
#if defined(EMU_C68K)\r
-static __inline int PicoMemBase(u32 pc)\r
+void cyclone_crashed(u32 pc, struct Cyclone *context)\r
{\r
- int membase=0;\r
-\r
- if (pc<Pico.romsize+4)\r
- {\r
- membase=(int)Pico.rom; // Program Counter in Rom\r
- }\r
- else if ((pc&0xe00000)==0xe00000)\r
- {\r
- membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram\r
- }\r
- else\r
- {\r
- // Error - Program Counter is invalid\r
- membase=(int)Pico.rom;\r
- }\r
-\r
- return membase;\r
+ elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x\n",\r
+ context == &PicoCpuCM68k ? 'm' : 's', pc);\r
+ context->membase = (u32)Pico.rom;\r
+ context->pc = (u32)Pico.rom + Pico.romsize;\r
}\r
#endif\r
\r
-\r
-PICO_INTERNAL u32 PicoCheckPc(u32 pc)\r
-{\r
- u32 ret=0;\r
-#if defined(EMU_C68K)\r
- pc-=PicoCpuCM68k.membase; // Get real pc\r
-// pc&=0xfffffe;\r
- pc&=~1;\r
- if ((pc<<8) == 0)\r
- {\r
- elprintf(EL_STATUS|EL_ANOMALY, "%i:%03i: game crash detected @ %06x\n",\r
- Pico.m.frame_count, Pico.m.scanline, SekPc);\r
- return (int)Pico.rom + Pico.romsize; // common crash condition, may happen with bad ROMs\r
- }\r
-\r
- PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r
- PicoCpuCM68k.membase-=pc&0xff000000;\r
-\r
- ret = PicoCpuCM68k.membase+pc;\r
-#endif\r
- return ret;\r
-}\r
-\r
-\r
-PICO_INTERNAL void PicoInitPc(u32 pc)\r
-{\r
- PicoCheckPc(pc);\r
-}\r
-\r
// -----------------------------------------------------------------\r
// memmap helpers\r
\r
-static int PadRead(int i)\r
+#ifndef _ASM_MEMORY_C\r
+static\r
+#endif\r
+int PadRead(int i)\r
{\r
int pad,value,data_reg;\r
pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
return value; // will mirror later\r
}\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
static u32 io_ports_read(u32 a)\r
{\r
u32 d;\r
return d;\r
}\r
\r
-static void io_ports_write(u32 a, u32 d)\r
+static void NOINLINE io_ports_write(u32 a, u32 d)\r
{\r
a = (a>>1) & 0xf;\r
\r
Pico.m.padTHPhase[a - 1]++;\r
}\r
\r
- // cartain IO ports can be used as RAM\r
+ // certain IO ports can be used as RAM\r
Pico.ioports[a] = d;\r
}\r
\r
-static void ctl_write_z80busreq(u32 d)\r
+#endif // _ASM_MEMORY_C\r
+\r
+void NOINLINE ctl_write_z80busreq(u32 d)\r
{\r
d&=1; d^=1;\r
elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
else\r
{\r
z80stopCycle = SekCyclesDone();\r
- if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset)\r
+ if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {\r
+ pprof_start(m68k);\r
PicoSyncZ80(z80stopCycle);\r
+ pprof_end_sub(m68k);\r
+ }\r
}\r
Pico.m.z80Run = d;\r
}\r
}\r
\r
-static void ctl_write_z80reset(u32 d)\r
+void NOINLINE ctl_write_z80reset(u32 d)\r
{\r
d&=1; d^=1;\r
elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
{\r
if (d)\r
{\r
- if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run)\r
+ if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {\r
+ pprof_start(m68k);\r
PicoSyncZ80(SekCyclesDone());\r
+ pprof_end_sub(m68k);\r
+ }\r
YM2612ResetChip();\r
timers_reset();\r
}\r
\r
// -----------------------------------------------------------------\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
// cart (save) RAM area (usually 0x200000 - ...)\r
static u32 PicoRead8_sram(u32 a)\r
{\r
static u32 PicoRead16_sram(u32 a)\r
{\r
u32 d;\r
- if (SRam.end >= a && a >= SRam.start && (Pico.m.sram_reg & SRR_MAPPED))\r
+ if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
{\r
if (SRam.flags & SRF_EEPROM)\r
d = EEPROM_read();\r
return m68k_unmapped_read16(a);\r
}\r
\r
+#endif // _ASM_MEMORY_C\r
+\r
static void PicoWrite8_sram(u32 a, u32 d)\r
{\r
if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
SN76496Write(d);\r
return;\r
}\r
-#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
{\r
Pico.m.z80_bank68k >>= 1;\r
elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
return;\r
}\r
-#endif\r
elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
}\r
\r
PicoWrite8_z80(a, d >> 8);\r
}\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
// IO/control area (0xa10000 - 0xa1ffff)\r
u32 PicoRead8_io(u32 a)\r
{\r
d = Pico.m.rotate++;\r
d ^= d << 6;\r
\r
- // bit8 seems to be readable in this range\r
- if ((a & 0xfc01) == 0x1000)\r
- d &= ~0x01;\r
+ if ((a & 0xfc00) == 0x1000) {\r
+ // bit8 seems to be readable in this range\r
+ if (!(a & 1))\r
+ d &= ~0x01;\r
\r
- if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
- d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
- elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)\r
+ d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;\r
+ elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ }\r
+ goto end;\r
+ }\r
+\r
+ if (PicoOpt & POPT_EN_32X) {\r
+ d = PicoRead8_32x(a);\r
goto end;\r
}\r
\r
\r
if ((a & 0xffe0) == 0x0000) { // I/O ports\r
d = io_ports_read(a);\r
+ d |= d << 8;\r
goto end;\r
}\r
\r
d ^= (d << 5) ^ (d << 8);\r
\r
// bit8 seems to be readable in this range\r
- if ((a & 0xfc00) == 0x1000)\r
+ if ((a & 0xfc00) == 0x1000) {\r
d &= ~0x0100;\r
\r
- if ((a & 0xff00) == 0x1100) { // z80 busreq\r
- d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
- elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ if ((a & 0xff00) == 0x1100) { // z80 busreq\r
+ d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;\r
+ elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);\r
+ }\r
+ goto end;\r
+ }\r
+\r
+ if (PicoOpt & POPT_EN_32X) {\r
+ d = PicoRead16_32x(a);\r
goto end;\r
}\r
\r
Pico.m.sram_reg |= (u8)(d & 3);\r
return;\r
}\r
+ if (PicoOpt & POPT_EN_32X) {\r
+ PicoWrite8_32x(a, d);\r
+ return;\r
+ }\r
+\r
m68k_unmapped_write8(a, d);\r
}\r
\r
Pico.m.sram_reg |= (u8)(d & 3);\r
return;\r
}\r
+ if (PicoOpt & POPT_EN_32X) {\r
+ PicoWrite16_32x(a, d);\r
+ return;\r
+ }\r
m68k_unmapped_write16(a, d);\r
}\r
\r
+#endif // _ASM_MEMORY_C\r
+\r
// VDP area (0xc00000 - 0xdfffff)\r
// TODO: verify if lower byte goes to PSG on word writes\r
static u32 PicoRead8_vdp(u32 a)\r
\r
// Setup memory callbacks:\r
#ifdef EMU_C68K\r
- PicoCpuCM68k.checkpc = PicoCheckPc;\r
- PicoCpuCM68k.fetch8 = PicoCpuCM68k.read8 = m68k_read8;\r
- PicoCpuCM68k.fetch16 = PicoCpuCM68k.read16 = m68k_read16;\r
- PicoCpuCM68k.fetch32 = PicoCpuCM68k.read32 = m68k_read32;\r
- PicoCpuCM68k.write8 = m68k_write8;\r
- PicoCpuCM68k.write16 = m68k_write16;\r
- PicoCpuCM68k.write32 = m68k_write32;\r
+ PicoCpuCM68k.read8 = (void *)m68k_read8_map;\r
+ PicoCpuCM68k.read16 = (void *)m68k_read16_map;\r
+ PicoCpuCM68k.read32 = (void *)m68k_read16_map;\r
+ PicoCpuCM68k.write8 = (void *)m68k_write8_map;\r
+ PicoCpuCM68k.write16 = (void *)m68k_write16_map;\r
+ PicoCpuCM68k.write32 = (void *)m68k_write16_map;\r
+ PicoCpuCM68k.checkpc = NULL; /* unused */\r
+ PicoCpuCM68k.fetch8 = NULL;\r
+ PicoCpuCM68k.fetch16 = NULL;\r
+ PicoCpuCM68k.fetch32 = NULL;\r
#endif\r
#ifdef EMU_F68K\r
PicoCpuFM68k.read_byte = m68k_read8;\r
if (xcycles >= timer_b_next_oflow) \\r
ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2\r
\r
-static u32 MEMH_FUNC ym2612_read_local_z80(void)\r
+static u32 ym2612_read_local_z80(void)\r
{\r
int xcycles = z80_cyclesDone() << 8;\r
\r
// -----------------------------------------------------------------\r
// z80 memhandlers\r
\r
-static unsigned char MEMH_FUNC z80_md_vdp_read(unsigned short a)\r
+static unsigned char z80_md_vdp_read(unsigned short a)\r
{\r
// TODO?\r
elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);\r
return 0xff;\r
}\r
\r
-static unsigned char MEMH_FUNC z80_md_bank_read(unsigned short a)\r
+static unsigned char z80_md_bank_read(unsigned short a)\r
{\r
- extern unsigned int PicoReadM68k8(unsigned int a);\r
unsigned int addr68k;\r
unsigned char ret;\r
\r
return ret;\r
}\r
\r
-static void MEMH_FUNC z80_md_ym2612_write(unsigned int a, unsigned char data)\r
+static void z80_md_ym2612_write(unsigned int a, unsigned char data)\r
{\r
if (PicoOpt & POPT_EN_FM)\r
emustatus |= ym2612_write_local(a, data, 1) & 1;\r
}\r
\r
-static void MEMH_FUNC z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
+static void z80_md_vdp_br_write(unsigned int a, unsigned char data)\r
{\r
// TODO: allow full VDP access\r
if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17\r
elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
-static void MEMH_FUNC z80_md_bank_write(unsigned int a, unsigned char data)\r
+static void z80_md_bank_write(unsigned int a, unsigned char data)\r
{\r
- extern void PicoWriteM68k8(unsigned int a, unsigned char d);\r
unsigned int addr68k;\r
\r
addr68k = Pico.m.z80_bank68k << 15;\r
drZ80.z80_out = z80_md_out;\r
#endif\r
#ifdef _USE_CZ80\r
- Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (UINT32)Pico.zram); // main RAM\r
- Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (UINT32)Pico.zram); // mirror\r
+ Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM\r
+ Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror\r
Cz80_Set_INPort(&CZ80, z80_md_in);\r
Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
#endif\r