\r
PicoInitMCD();\r
PicoSVPInit();\r
+ Pico32xInit();\r
}\r
\r
// to be called once on emu exit\r
if (PicoAHW & PAHW_MCD)\r
PicoPowerMCD();\r
\r
+ if (!(PicoOpt & POPT_DIS_32X))\r
+ PicoPower32x();\r
+\r
PicoReset();\r
}\r
\r
if (!(PicoOpt & POPT_DIS_IDLE_DET))\r
SekInitIdleDet();\r
\r
+ if (!(PicoOpt & POPT_DIS_32X)) {\r
+ PicoReset32x();\r
+ return 0;\r
+ }\r
+\r
// reset sram state; enable sram access by default if it doesn't overlap with ROM\r
Pico.m.sram_reg = 0;\r
if ((SRam.flags & SRF_EEPROM) || Pico.romsize <= SRam.start)\r
return;\r
}\r
\r
+ // TODO: MCD+32X\r
if (PicoAHW & PAHW_MCD) {\r
PicoFrameMCD();\r
return;\r
}\r
\r
+ if (PicoAHW & PAHW_32X) {\r
+ PicoFrame32x();\r
+ return;\r
+ }\r
+\r
//if(Pico.video.reg[12]&0x2) Pico.video.status ^= 0x10; // change odd bit in interlace mode\r
\r
PicoFrameStart();\r