typedef unsigned char (z80_read_f)(unsigned short a);\r
typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
\r
+// ----------------------- SH2 CPU -----------------------\r
+\r
+#include "cpu/sh2mame/sh2.h"\r
+\r
+SH2 msh2, ssh2;\r
+#define ash2_pc() msh2.ppc\r
+#define ash2_end_run(after) sh2_icount = after\r
+\r
+#define msh2_pc() msh2.ppc\r
+#define ssh2_pc() ssh2.ppc\r
+\r
+#define msh2_reg(x) msh2.r[x]\r
+#define ssh2_reg(x) ssh2.r[x]\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
// 32X\r
-#define P32XV_nPAL (1<<15)\r
-#define P32XV_PRI (1<< 7)\r
-#define P32XV_Mx (3<< 0)\r
+#define P32XS_FM (1<<15)\r
+#define P32XS2_ADEN (1<< 9)\r
+\r
+#define P32XV_nPAL (1<<15)\r
+#define P32XV_PRI (1<< 7)\r
+#define P32XV_Mx (3<< 0)\r
+\r
+#define P32XV_VBLK (1<<15)\r
+#define P32XV_HBLK (1<<14)\r
+#define P32XV_PEN (1<<13)\r
+#define P32XV_nFEN (1<< 1)\r
+#define P32XV_FS (1<< 0)\r
\r
-#define P32XV_VBLK (1<<15)\r
-#define P32XV_HBLK (1<<14)\r
-#define P32XV_PEN (1<<13)\r
-#define P32XV_nFEN (1<< 1)\r
-#define P32XV_FS (1<< 0)\r
+#define P32XF_68KPOLL (1 << 0)\r
+#define P32XF_MSH2POLL (1 << 1)\r
+#define P32XF_SSH2POLL (1 << 2)\r
\r
struct Pico32x\r
{\r
unsigned char pending_fb;\r
unsigned char dirty_pal;\r
unsigned char pad[2];\r
+ unsigned int emu_flags;\r
};\r
\r
struct Pico32xMem\r
unsigned char sdram[0x40000];\r
unsigned short dram[2][0x20000/2]; // AKA fb\r
unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
+ unsigned char sh2_rom_m[0x800];\r
+ unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
};\r