extern "C" {\r
#endif\r
\r
+#ifdef _MSC_VER\r
+#define snprintf _snprintf\r
+#define strcasecmp _stricmp\r
+#define strncasecmp _strnicmp\r
+#endif\r
\r
// ----------------------- 68000 CPU -----------------------\r
#ifdef EMU_C68K\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
\r
+#define SekNotPolling PicoCpuCM68k.not_pol\r
+#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
+\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
#define SekIrqLevel PicoCpuCM68k.irq\r
\r
#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
#define SekShouldInterrupt() fm68k_would_interrupt()\r
\r
+#define SekNotPolling PicoCpuFM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
+\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
\r
+#define SekNotPolling PicoCpuMM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
+\r
#define SekInterrupt(irq) { \\r
void *oldcontext = m68ki_cpu_p; \\r
m68k_set_context(&PicoCpuMM68k); \\r
#define SekCyclesBurn(c) SekCycleCnt += c\r
#define SekCyclesBurnRun(c) { \\r
SekCyclesLeft -= c; \\r
- if (SekCyclesLeft < 0) \\r
- SekCyclesLeft = 0; \\r
}\r
\r
// note: sometimes may extend timeslice to delay an irq\r
#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
#define z80_int() drZ80.Z80_IRQ = 1\r
+#define z80_int() drZ80.Z80_IRQ = 1\r
+#define z80_nmi() drZ80.Z80IF |= 8\r
\r
#define z80_cyclesLeft drZ80.cycles\r
#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
+#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
\r
#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
#define z80_run(cycles) (cycles)\r
#define z80_run_nr(cycles)\r
#define z80_int()\r
+#define z80_nmi()\r
\r
#endif\r
\r
unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
unsigned short z80_bank68k; // 0a\r
unsigned short pad0;\r
- unsigned char pad1;\r
+ unsigned char ncart_in; // 0e !cart_in\r
unsigned char z80_reset; // 0f z80 reset held\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
unsigned short eeprom_addr; // EEPROM address register\r
{\r
unsigned char carthw[0x10];\r
unsigned char io_ctl;\r
- unsigned char pad[0x4f];\r
+ unsigned char nmi_state;\r
+ unsigned char pad[0x4e];\r
};\r
\r
// some assembly stuff depend on these, do not touch!\r
};\r
\r
// MCD\r
-#include "cd/cd_sys.h"\r
-#include "cd/LC89510.h"\r
-#include "cd/gfx_cd.h"\r
+#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
\r
struct mcd_pcm\r
{\r
unsigned char enabled; // reg8\r
unsigned char cur_ch;\r
unsigned char bank;\r
- int pad1;\r
+ unsigned int update_cycles;\r
\r
struct pcm_chan // 08, size 0x10\r
{\r
} ch[8];\r
};\r
\r
+#define PCD_ST_S68K_RST 1\r
+\r
struct mcd_misc\r
{\r
- unsigned short hint_vector;\r
- unsigned char busreq;\r
- unsigned char s68k_pend_ints;\r
- unsigned int state_flags; // 04\r
- unsigned int stopwatch_base_c;\r
- unsigned short m68k_poll_a;\r
- unsigned short m68k_poll_cnt;\r
- unsigned short s68k_poll_a;\r
- unsigned short s68k_poll_cnt;\r
- unsigned int s68k_poll_clk;\r
- unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
- unsigned char dmna_ret_2m;\r
- unsigned short pad3;\r
- int pad4[9];\r
+ unsigned short hint_vector;\r
+ unsigned char busreq; // not s68k_regs[1]\r
+ unsigned char s68k_pend_ints;\r
+ unsigned int state_flags; // 04\r
+ unsigned int stopwatch_base_c;\r
+ unsigned short m68k_poll_a;\r
+ unsigned short m68k_poll_cnt;\r
+ unsigned short s68k_poll_a;\r
+ unsigned short s68k_poll_cnt;\r
+ unsigned int s68k_poll_clk;\r
+ unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
+ unsigned char dmna_ret_2m;\r
+ unsigned char need_sync;\r
+ unsigned char pad3;\r
+ int pad4[9];\r
};\r
\r
typedef struct\r
{\r
- unsigned char bios[0x20000]; // 000000: 128K\r
- union { // 020000: 512K\r
- unsigned char prg_ram[0x80000];\r
- unsigned char prg_ram_b[4][0x20000];\r
- };\r
- union { // 0a0000: 256K\r
- struct {\r
- unsigned char word_ram2M[0x40000];\r
- unsigned char unused0[0x20000];\r
- };\r
- struct {\r
- unsigned char unused1[0x20000];\r
- unsigned char word_ram1M[2][0x20000];\r
- };\r
- };\r
- union { // 100000: 64K\r
- unsigned char pcm_ram[0x10000];\r
- unsigned char pcm_ram_b[0x10][0x1000];\r
- };\r
- // FIXME: should be short\r
- unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
- unsigned char bram[0x2000]; // 110200: 8K\r
- struct mcd_misc m; // 112200: misc\r
- struct mcd_pcm pcm; // 112240:\r
- _scd_toc TOC; // not to be saved\r
- CDD cdd;\r
- CDC cdc;\r
- _scd scd;\r
- Rot_Comp rot_comp;\r
+ unsigned char bios[0x20000]; // 000000: 128K\r
+ union { // 020000: 512K\r
+ unsigned char prg_ram[0x80000];\r
+ unsigned char prg_ram_b[4][0x20000];\r
+ };\r
+ union { // 0a0000: 256K\r
+ struct {\r
+ unsigned char word_ram2M[0x40000];\r
+ unsigned char unused0[0x20000];\r
+ };\r
+ struct {\r
+ unsigned char unused1[0x20000];\r
+ unsigned char word_ram1M[2][0x20000];\r
+ };\r
+ };\r
+ union { // 100000: 64K\r
+ unsigned char pcm_ram[0x10000];\r
+ unsigned char pcm_ram_b[0x10][0x1000];\r
+ };\r
+ unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
+ unsigned char bram[0x2000]; // 110200: 8K\r
+ struct mcd_misc m; // 112200: misc\r
+ struct mcd_pcm pcm; // 112240:\r
+ void *cdda_stream;\r
+ int cdda_type;\r
+ int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
+ int pcm_mixpos;\r
+ char pcm_mixbuf_dirty;\r
+ char pcm_regs_dirty;\r
} mcd_state;\r
\r
// XXX: this will need to be reworked for cart+cd support.\r
\r
// 32X\r
#define P32XS_FM (1<<15)\r
+#define P32XS_nCART (1<< 8)\r
#define P32XS_REN (1<< 7)\r
#define P32XS_nRES (1<< 1)\r
#define P32XS_ADEN (1<< 0)\r
// pico/memory.c\r
PICO_INTERNAL void PicoMemSetupPico(void);\r
\r
+// cd/cdc.c\r
+void cdc_init(void);\r
+void cdc_reset(void);\r
+int cdc_context_save(unsigned char *state);\r
+int cdc_context_load(unsigned char *state);\r
+int cdc_context_load_old(unsigned char *state);\r
+void cdc_dma_update(void);\r
+int cdc_decoder_update(unsigned char header[4]);\r
+void cdc_reg_w(unsigned char data);\r
+unsigned char cdc_reg_r(void);\r
+unsigned short cdc_host_r(void);\r
+\r
+// cd/cdd.c\r
+void cdd_reset(void);\r
+int cdd_context_save(unsigned char *state);\r
+int cdd_context_load(unsigned char *state);\r
+int cdd_context_load_old(unsigned char *state);\r
+void cdd_read_data(unsigned char *dst);\r
+void cdd_read_audio(unsigned int samples);\r
+void cdd_update(void);\r
+void cdd_process(void);\r
+\r
+// cd/cd_image.c\r
+int load_cd_image(const char *cd_img_name, int *type);\r
+\r
+// cd/gfx.c\r
+void gfx_init(void);\r
+void gfx_start(unsigned int base);\r
+void gfx_update(unsigned int cycles);\r
+int gfx_context_save(unsigned char *state);\r
+int gfx_context_load(const unsigned char *state);\r
+\r
+// cd/gfx_dma.c\r
+void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
+\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
+unsigned int PicoRead8_mcd_io(unsigned int a);\r
+unsigned int PicoRead16_mcd_io(unsigned int a);\r
+void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
+void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
void pcd_state_loaded_mem(void);\r
\r
// pico.c\r
extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
+void pcd_prepare_frame(void);\r
unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
+void pcd_run_cpus(int m68k_cycles);\r
+void pcd_soft_reset(void);\r
void pcd_state_loaded(void);\r
\r
+// cd/pcm.c\r
+void pcd_pcm_sync(unsigned int to);\r
+void pcd_pcm_update(int *buffer, int length, int stereo);\r
+void pcd_pcm_write(unsigned int a, unsigned int d);\r
+unsigned int pcd_pcm_read(unsigned int a);\r
+\r
// pico/pico.c\r
PICO_INTERNAL void PicoInitPico(void);\r
PICO_INTERNAL void PicoReratePico(void);\r
PICO_INTERNAL void SekInitS68k(void);\r
PICO_INTERNAL int SekResetS68k(void);\r
PICO_INTERNAL int SekInterruptS68k(int irq);\r
+void SekInterruptClearS68k(int irq);\r
\r
// sound/sound.c\r
-PICO_INTERNAL void cdda_start_play();\r
extern short cdda_out_buffer[2*1152];\r
extern int PsndLen_exc_cnt;\r
extern int PsndLen_exc_add;\r
extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
extern int timer_b_next_oflow, timer_b_step;\r
\r
+void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
+\r
void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
void ym2612_pack_state(void);\r
void ym2612_unpack_state(void);\r
\r
\r
// videoport.c\r
+extern int line_base_cycles;\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
\r
// misc.c\r
-PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
+PICO_INTERNAL_ASM void pmemcpy16(unsigned short *dest, unsigned short *src, int count);\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
\r
-// cd/buffering.c\r
-PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
-\r
// sound/sound.c\r
PICO_INTERNAL void PsndReset(void);\r
PICO_INTERNAL void PsndDoDAC(int line_to);\r
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
-void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
-void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
-void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
#else\r
#define Pico32xInit()\r
#endif\r
\r
/* avoid dependency on newer glibc */\r
-static __inline int isspace_(int c)\r
+static INLINE int isspace_(int c)\r
{\r
return (0x09 <= c && c <= 0x0d) || c == ' ';\r
}\r
#define cdprintf(x...)\r
#endif\r
\r
-#ifdef __i386__\r
+#if defined(__GNUC__) && defined(__i386__)\r
#define REGPARM(x) __attribute__((regparm(x)))\r
#else\r
#define REGPARM(x)\r