bool light = true; /* lighting */
bool blend = true; /* blending */
+bool fb_dirty = false;
+
bool enableAbbeyHack = false; /* Abe's Odyssey hack */
u8 BLEND_MODE;
u8 TEXT_MODE;
u32 tInc, tMsk;
GPUPacket PacketBuffer;
-u16 GPU_FrameBuffer[FRAME_BUFFER_SIZE/2] __attribute__((aligned(16))); // FRAME_BUFFER_SIZE is defined in bytes
+// FRAME_BUFFER_SIZE is defined in bytes; 512K is guard memory for out of range reads
+u16 GPU_FrameBuffer[(FRAME_BUFFER_SIZE+512*1024)/2] __attribute__((aligned(16)));
u32 GPU_GP1;
///////////////////////////////////////////////////////////////////////////////
if (bWrite)
{
p2->GPU_gp1 = GPU_GP1;
+ memset(p2->Control, 0, sizeof(p2->Control));
+ // save resolution and registers for P.E.Op.S. compatibility
+ p2->Control[3] = (3 << 24) | ((GPU_GP1 >> 23) & 1);
+ p2->Control[4] = (4 << 24) | ((GPU_GP1 >> 29) & 3);
+ p2->Control[5] = (5 << 24) | (DisplayArea[0] | (DisplayArea[1] << 10));
+ p2->Control[6] = (6 << 24) | (2560 << 12);
+ p2->Control[7] = (7 << 24) | (DisplayArea[4] | (DisplayArea[5] << 10));
+ p2->Control[8] = (8 << 24) | ((GPU_GP1 >> 17) & 0x3f) | ((GPU_GP1 >> 10) & 0x40);
memcpy(p2->FrameBuffer, (u16*)GPU_FrameBuffer, FRAME_BUFFER_SIZE);
return (1);
}
{
GPU_GP1 = p2->GPU_gp1;
memcpy((u16*)GPU_FrameBuffer, p2->FrameBuffer, FRAME_BUFFER_SIZE);
+ GPU_writeStatus((5 << 24) | p2->Control[5]);
+ GPU_writeStatus((7 << 24) | p2->Control[7]);
+ GPU_writeStatus((8 << 24) | p2->Control[8]);
+ gpuSetTexture(GPU_GP1);
return (1);
}
return (0);
}
GPU_GP1 = (GPU_GP1 | 0x14000000) & ~0x60000000;
+ fb_dirty = true;
pcsx4all_prof_end_with_resume(PCSX4ALL_PROF_GPU,PCSX4ALL_PROF_HW_WRITE);
pcsx4all_prof_resume(PCSX4ALL_PROF_CPU);
}
gpuCheckPacket(data);
}
GPU_GP1 |= 0x14000000;
+ fb_dirty = true;
pcsx4all_prof_end_with_resume(PCSX4ALL_PROF_GPU,PCSX4ALL_PROF_HW_WRITE);
pcsx4all_prof_resume(PCSX4ALL_PROF_CPU);
case 0x05:
DisplayArea[0] = (data & 0x000003FF); //(short)(data & 0x3ff);
DisplayArea[1] = ((data & 0x0007FC00)>>10); //(data & 0x000FFC00) >> 10; //(short)((data>>10)&0x1ff);
+ fb_dirty = true;
break;
case 0x07:
DisplayArea[4] = data & 0x000003FF; //(short)(data & 0x3ff);
DisplayArea[5] = (data & 0x000FFC00) >> 10; //(short)((data>>10) & 0x3ff);
+ fb_dirty = true;
break;
case 0x08:
{
DisplayArea[3] = VerticalResolution[(GPU_GP1 >> 19) & 3];
isPAL = (data & 0x08) ? true : false; // if 1 - PAL mode, else NTSC
}
+ fb_dirty = true;
break;
case 0x10:
switch (data & 0xffff) {
#else
#include "../../frontend/plugin_lib.h"
+#include "../../frontend/arm_utils.h"
extern "C" {
-extern void bgr555_to_rgb565(void *dst, void *src, int bytes);
-extern void bgr888_to_rgb888(void *dst, void *src, int bytes);
static const struct rearmed_cbs *cbs;
static void *screen_buf;
static s16 old_res_horz, old_res_vert, old_rgb24;
s16 isRGB24 = (GPU_GP1 & 0x00200000) ? 1 : 0;
s16 h0, x0, y0, w0, h1;
- u8 *dest = (u8 *)screen_buf;
u16 *srcs;
+ u8 *dest;
x0 = DisplayArea[0] & ~3; // alignment needed by blitter
y0 = DisplayArea[1];
h1 = DisplayArea[5] - DisplayArea[4]; // display needed
if (h0 == 480) h1 = Min2(h1*2,480);
+ if (h1 <= 0)
+ return;
+
if (w0 != old_res_horz || h1 != old_res_vert || isRGB24 != old_rgb24)
{
old_res_horz = w0;
old_res_vert = h1;
old_rgb24 = (s16)isRGB24;
- cbs->pl_fbdev_set_mode(w0, h1, isRGB24 ? 24 : 16);
+ screen_buf = cbs->pl_fbdev_set_mode(w0, h1, isRGB24 ? 24 : 16);
}
+ dest = (u8 *)screen_buf;
if (isRGB24)
{
+#ifndef MAEMO
for (; h1-- > 0; dest += w0 * 3, srcs += 1024)
{
bgr888_to_rgb888(dest, srcs, w0 * 3);
}
+#else
+ for (; h1-- > 0; dest += w0 * 2, srcs += 1024)
+ {
+ bgr888_to_rgb565(dest, srcs, w0 * 3);
+ }
+#endif
}
else
{
// Interlace bit toggle
GPU_GP1 ^= 0x80000000;
- if (!((GPU_GP1&0x08000000) || (GPU_GP1&0x00800000)))
+ if (!fb_dirty || (GPU_GP1&0x08800000))
+ return;
+
+ if (!isSkip) {
blit();
+
+ fb_dirty = false;
+ if (*cbs->fskip_option)
+ isSkip = true;
+ }
+ else
+ isSkip = false;
}
long GPUopen(unsigned long *, char *, char *)