X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=Pico%2FMisc.c;h=8e89a4f26b36255034d8d4f31ef7137b96dad560;hb=7969166ef66a8623cb4d8c609eb6e67314aefd79;hp=887e90cc3ee49f7b7a59afadac9cd272fa2623e4;hpb=cc68a136aa179a5f32fe40208371eb9c2b0aadae;p=picodrive.git diff --git a/Pico/Misc.c b/Pico/Misc.c index 887e90c..8e89a4f 100644 --- a/Pico/Misc.c +++ b/Pico/Misc.c @@ -85,7 +85,7 @@ const unsigned char hcounts_32[] = { 0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d, }; -// vcounter values for PicoFrameSimple +// vcounter values for PicoFrameSimple const unsigned short vcounts[] = { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, @@ -141,11 +141,11 @@ unsigned int lastSSRamWrite = 0xffff0000; // sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=type(1==uses 0x200000 for SCL and 2K bytes), // d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA) -void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) +PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) { unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave; - //dprintf("[%02x]", d); + //printf("EEPROM write %i\n", d&3); sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ... (d=word count detected, w=words(0==use 2 words, else 1)) saddr&=0x1fff; @@ -154,11 +154,11 @@ void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) if((sreg & 1) && !(d&1)) { // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter //dprintf("-start-"); - if(!(sreg&0x8000) && scyc >= 9) { - if(scyc != 28) sreg |= 0x4000; // 1 word + if(!(sreg&0x8000) && scyc >= 9) { + if(scyc != 28) sreg |= 0x4000; // 1 word //dprintf("detected word count: %i", scyc==28 ? 2 : 1); - sreg |= 0x8000; - } + sreg |= 0x8000; + } //saddr = 0; scyc = 0; sreg |= 8; @@ -171,30 +171,30 @@ void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) else if((sreg & 8) && !(sreg & 2) && (d&2)) { // we are started and SCL went high - next cycle scyc++; // pre-increment - if(sreg & 0x20) { + if(sreg & 0x20) { // X24C02+ - if((ssa&1) && scyc == 18) { - scyc = 9; - saddr++; // next address in read mode - if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask - } - else if((sreg&0x4000) && scyc == 27) scyc = 18; - else if(scyc == 36) scyc = 27; - } else { - // X24C01 + if((ssa&1) && scyc == 18) { + scyc = 9; + saddr++; // next address in read mode + if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask + } + else if((sreg&0x4000) && scyc == 27) scyc = 18; + else if(scyc == 36) scyc = 27; + } else { + // X24C01 if(scyc == 18) { scyc = 9; // wrap if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode - } - } - //dprintf("scyc: %i", scyc); + } + } + //dprintf("scyc: %i", scyc); } else if((sreg & 8) && (sreg & 2) && !(d&2)) { // we are started and SCL went low (falling edge) if(sreg & 0x20) { - // X24C02+ - if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles - else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) { + // X24C02+ + if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles + else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) { if(!(ssa&1)) { // data write unsigned char *pm=SRam.data+saddr; @@ -208,18 +208,18 @@ void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) } else if(scyc > 9) { if(!(ssa&1)) { // we latch another addr bit - saddr<<=1; - if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask - saddr|=d&1; + saddr<<=1; + if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask + saddr|=d&1; //if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr); - } + } } else { - // slave address - ssa<<=1; ssa|=d&1; + // slave address + ssa<<=1; ssa|=d&1; //if(scyc==8) dprintf("slave done: %x", ssa); } - } else { - // X24C01 + } else { + // X24C01 if(scyc == 9); // ACK cycle, do nothing else if(scyc > 9) { if(!(saddr&1)) { @@ -237,7 +237,7 @@ void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) saddr<<=1; saddr|=d&1; saddr&=0xff; //if(scyc==8) dprintf("addr done: %x", saddr>>1); } - } + } } sreg &= ~3; sreg |= d&3; // remember SCL and SDA @@ -247,7 +247,7 @@ void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA) Pico.m.sram_slave= (unsigned char) ssa; } -unsigned int SRAMReadEEPROM() +PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void) { unsigned int shift, d=0; unsigned int sreg, saddr, scyc, ssa; @@ -265,24 +265,24 @@ unsigned int SRAMReadEEPROM() // started and first command word received shift = 17-scyc; if(sreg & 0x20) { - // X24C02+ + // X24C02+ if(ssa&1) { //dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg); - d = (SRam.data[saddr]>>shift)&1; - } - } else { - // X24C01 + d = (SRam.data[saddr]>>shift)&1; + } + } else { + // X24C01 if(saddr&1) { - d = (SRam.data[saddr>>1]>>shift)&1; - } - } + d = (SRam.data[saddr>>1]>>shift)&1; + } + } } //else dprintf("r ack"); return d; } -void SRAMUpdPending(unsigned int a, unsigned int d) +PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d) { unsigned int sreg = Pico.m.sram_reg; @@ -303,3 +303,36 @@ void SRAMUpdPending(unsigned int a, unsigned int d) Pico.m.sram_reg = (unsigned char) sreg; } + + +#ifndef _ASM_MISC_C +PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count) +{ + while (count--) + *dest++ = *src++; +} + + +PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count) +{ + unsigned char *src_ = src; + + for (; count; count--, src_ += 2) + *dest++ = (src_[0] << 8) | src_[1]; +} + + +PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count) +{ + while (count--) + *dest++ = *src++; +} + + +PICO_INTERNAL_ASM void memset32(int *dest, int c, int count) +{ + while (count--) + *dest++ = c; +} +#endif +