X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=cpu%2FCyclone%2FOpBranch.cpp;h=d1c2391876b78d729614a03c8fee11f69a4c632d;hb=2270612aa7ee7d04549e95c2ab4d72f6aa67fa8d;hp=c24c7696e74f9d31ab376225337ecacdf3c818a8;hpb=85a36a57a816ac643ee5f982d774532a0ca4d58b;p=picodrive.git

diff --git a/cpu/Cyclone/OpBranch.cpp b/cpu/Cyclone/OpBranch.cpp
index c24c769..d1c2391 100644
--- a/cpu/Cyclone/OpBranch.cpp
+++ b/cpu/Cyclone/OpBranch.cpp
@@ -11,8 +11,7 @@ static void CheckPc(int reg)
   ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
   ot("  mov r4,r0\n");
 #else
-  if (reg != 4)
-    ot("  mov r4,r%i\n", reg);
+  ot("  bic r4,r%d,#1\n",reg); // we do not emulate address errors
 #endif
   ot("\n");
 }
@@ -158,11 +157,12 @@ int OpUnlk(int op)
 }
 
 // --------------------- Opcodes 0x4e70+ ---------------------
+// 01001110 01110ttt
 int Op4E70(int op)
 {
   int type=0;
 
-  type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr
+  type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr
 
   switch (type)
   {
@@ -193,7 +193,7 @@ int Op4E70(int op)
     case 6: // trapv
     OpStart(op,0x10); Cycles=4;
     ot("  tst r9,#0x10000000\n");
-    ot("  subne r5,r5,#%i\n",30);
+    ot("  subne r5,r5,#%i\n",34);
     ot("  movne r0,#0x1c ;@ TRAPV exception\n");
     ot("  blne Exception\n");
     OpEnd(0x10);
@@ -236,17 +236,17 @@ int OpJsr(int op)
   ot(";@ Jump - Get new PC from r0\n");
   if (op&0x40)
   {
-    // Jmp - Get new PC from r0
+    // Jmp - Get new PC from r11
     ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");
     ot("\n");
   }
   else
   {
     ot(";@ Jsr - Push old PC first\n");
-    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");
-    ot("  mov r1,r1,lsl #8\n");
     ot("  ldr r0,[r7,#0x3c]\n");
-    ot("  mov r1,r1,asr #8\n");
+    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");
+//    ot("  mov r1,r1,lsl #8\n");
+//    ot("  mov r1,r1,asr #8\n");
     ot(";@ Push r1 onto stack\n");
     ot("  sub r0,r0,#4 ;@ Predecrement A7\n");
     ot("  str r0,[r7,#0x3c] ;@ Save A7\n");
@@ -319,14 +319,25 @@ int OpDbra(int op)
 
     ot(";@ Check if Dn.w is -1\n");
     ot("  cmn r0,#1\n");
+
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
+    ot("  beq DbraMin1\n");
     ot("\n");
 
+    ot(";@ Get Branch offset:\n");
+    ot("  ldrsh r0,[r4]\n");
+    ot("  add r0,r4,r0 ;@ r4 = New PC\n");
+    CheckPc(0);
+#else
+    ot("\n");
     ot(";@ Get Branch offset:\n");
     ot("  ldrnesh r0,[r4]\n");
     ot("  addeq r4,r4,#2 ;@ Skip branch offset\n");
     ot("  subeq r5,r5,#4 ;@ additional cycles\n");
     ot("  addne r4,r4,r0 ;@ r4 = New PC\n");
+    ot("  bic r4,r4,#1\n"); // we do not emulate address errors
     ot("\n");
+#endif
     Cycles=12-2;
     OpEnd();
   }
@@ -342,6 +353,18 @@ int OpDbra(int op)
     OpEnd();
   }
 
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
+  if (op==0x51c8)
+  {
+    ot(";@ Dn.w is -1:\n");
+    ot("DbraMin1%s\n", ms?"":":");
+    ot("  add r4,r4,#2 ;@ Skip branch offset\n");
+    ot("\n");
+    Cycles=12+2;
+    OpEnd();
+  }
+#endif
+
   return 0;
 }
 
@@ -349,7 +372,7 @@ int OpDbra(int op)
 // Emit a Branch opcode 0110cccc nn  (cccc=condition)
 int OpBranch(int op)
 {
-  int size=0,use=0;
+  int size=0,use=0,checkpc=0;
   int offset=0;
   int cc=0;
   char *asr_r11="";
@@ -361,6 +384,7 @@ int OpBranch(int op)
   if (offset==0)  size=1;
   if (offset==-1) size=2;
 
+  if (size==2) size=0; // 000 model does not support long displacement
   if (size) use=op; // 16-bit or 32-bit
   else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
 
@@ -414,11 +438,11 @@ int OpBranch(int op)
   if (cc==1)
   {
     ot(";@ Bsr - remember old PC\n");
+    ot("  ldr r2,[r7,#0x3c]\n");
     ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");
     if (size) ot("  add r1,r1,#%d\n",1<<size);
-    ot("  mov r1,r1, lsl #8\n");
-    ot("  ldr r2,[r7,#0x3c]\n");
-    ot("  mov r1,r1, asr #8\n");
+//    ot("  mov r1,r1, lsl #8\n");
+//    ot("  mov r1,r1, asr #8\n");
     ot("\n");
     ot(";@ Push r1 onto stack\n");
     ot("  sub r0,r2,#4 ;@ Predecrement A7\n");
@@ -426,28 +450,27 @@ int OpBranch(int op)
     MemHandler(1,2);
     ot("\n");
     Cycles=18; // always 18
-    if (offset==0 || offset==-1)
-    {
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");
-      ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
-      CheckPc(0);
-    }
-    else
-      ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);
+  }
+
+  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
+
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
+  if (offset!=0 && offset!=-1) checkpc=1;
+#endif
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16
+  if (offset==0)  checkpc=1;
+#endif
+#if USE_CHECKPC_CALLBACK
+  if (offset==-1) checkpc=1;
+#endif
+  if (checkpc)
+  {
+    CheckPc(0);
   }
   else
   {
-    if (offset==0 || offset==-1)
-    {
-      ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");
-      CheckPc(0);
-    }
-    else
-    {
-      ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);
-      ot("\n");
-    }
+    ot("  bic r4,r0,#1\n"); // we do not emulate address errors
+    ot("\n");
   }
 
   OpEnd(size?0x10:0);
@@ -456,7 +479,7 @@ int OpBranch(int op)
   if (cc>=2&&(op&0xff00)==0x6200)
   {
     ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");
-    if (size) ot("  add r4,r4,#%d\n",8<<size);
+    if (size) ot("  add r4,r4,#%d\n",1<<size);
     Cycles+=(size==1) ? 2 : -2; // Branch not taken
     OpEnd(0);
   }