X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fsh2%2Fcompiler.c;h=0174bd69d747d37f0921e1dc78e1440c9ebec6e5;hb=d438a8dd8e1f9baf207caaccf1b7d9a53c5db4e0;hp=9861a859e04b16e0713f7dcfd09fdd44f93278df;hpb=1f1ff763e661bab664151c4821c65dad35777976;p=picodrive.git diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index 9861a85..0174bd6 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -1,5 +1,9 @@ /* - * vim:shiftwidth=2:expandtab + * SH2 recompiler + * (C) notaz, 2009,2010 + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. * * notes: * - tcache, block descriptor, link buffer overflows result in sh2_translate() @@ -37,7 +41,6 @@ #define LINK_BRANCHES 1 // limits (per block) -#define BLOCK_CYCLE_LIMIT 100 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) // max literal offset from the block end @@ -45,7 +48,20 @@ #define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4) #define MAX_LOCAL_BRANCHES 32 -// debug stuff { +/// +#define FETCH_OP(pc) \ + dr_pc_base[(pc) / 2] + +#define FETCH32(a) \ + ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1]) + +#ifdef DRC_SH2 + +// debug stuff +// 1 - ? +// 2 - ? +// 4 - log asm +// { #ifndef DRC_DEBUG #define DRC_DEBUG 0 #endif @@ -57,7 +73,7 @@ } #include "mame/sh2dasm.h" -#include +#include static int insns_compiled, hash_collisions, host_insn_count; #define COUNT_OP \ host_insn_count++ @@ -66,7 +82,7 @@ static int insns_compiled, hash_collisions, host_insn_count; #define dbg(...) #endif -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) static u8 *tcache_dsm_ptrs[3]; static char sh2dasm_buff[64]; #define do_host_disasm(tcid) \ @@ -76,11 +92,11 @@ static char sh2dasm_buff[64]; #define do_host_disasm(x) #endif -#if (DRC_DEBUG & 4) || defined(PDB) +#if (DRC_DEBUG & 8) || defined(PDB) static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr) { if (block != NULL) { - dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', + dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', sh2->pc, block, (signed int)sr >> 12); pdb_step(sh2, sh2->pc); } @@ -111,7 +127,7 @@ typedef struct block_desc_ { u32 addr; // SH2 PC address void *tcache_ptr; // translated block for above PC struct block_desc_ *next; // next block with the same PC hash -#if (DRC_DEBUG & 1) +#if (DRC_DEBUG & 2) int refcount; #endif } block_desc; @@ -155,16 +171,16 @@ typedef struct { // note: reg_temp[] must have at least the amount of // registers used by handlers in worst case (currently 4) -#ifdef ARM +#ifdef __arm__ #include "../drc/emit_arm.c" static const int reg_map_g2h[] = { 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 9, - -1, -1, -1, 10, - -1, -1, -1, -1, + -1, -1, -1, 9, // r12 .. sp + -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR, + -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL, }; static temp_reg_t reg_temp[] = { @@ -233,41 +249,7 @@ static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d); static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2); -extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); - // address space stuff -static void *dr_get_pc_base(u32 pc, int is_slave) -{ - void *ret = NULL; - u32 mask = 0; - - if ((pc & ~0x7ff) == 0) { - // BIOS - ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; - mask = 0x7ff; - } - else if ((pc & 0xfffff000) == 0xc0000000) { - // data array - ret = Pico32xMem->data_array[is_slave]; - mask = 0xfff; - } - else if ((pc & 0xc6000000) == 0x06000000) { - // SDRAM - ret = Pico32xMem->sdram; - mask = 0x03ffff; - } - else if ((pc & 0xc6000000) == 0x02000000) { - // ROM - ret = Pico.rom; - mask = 0x3fffff; - } - - if (ret == NULL) - return (void *)-1; // NULL is valid value - - return (char *)ret - (pc & ~mask); -} - static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) { int poffs = -1; @@ -344,7 +326,7 @@ static void REGPARM(1) flush_tcache(int tcid) } else memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; #endif } @@ -357,7 +339,7 @@ static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id) int cnt = block_link_counts[tcache_id]; if (cnt >= block_max_counts[tcache_id] * 2) { - printf("bl overflow for tcache %d\n", tcache_id); + dbg(1, "bl overflow for tcache %d\n", tcache_id); return -1; } @@ -377,7 +359,7 @@ static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id) bd = dr_get_bd(addr, is_slave, &tcache_id); if (bd != NULL) { - dbg(1, "block override for %08x", addr); + dbg(2, "block override for %08x", addr); bd->tcache_ptr = tcache_ptr; *blk_id = bd - block_tables[tcache_id]; return bd; @@ -385,7 +367,7 @@ static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id) bcount = &block_counts[tcache_id]; if (*bcount >= block_max_counts[tcache_id]) { - printf("bd overflow for tcache %d\n", tcache_id); + dbg(1, "bd overflow for tcache %d", tcache_id); return NULL; } if (*bcount == 0) @@ -400,7 +382,7 @@ static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id) if ((addr & 0xc6000000) == 0x02000000) { // ROM bd->next = HASH_FUNC(hash_table, addr); HASH_FUNC(hash_table, addr) = bd; -#if (DRC_DEBUG & 1) +#if (DRC_DEBUG & 2) if (bd->next != NULL) { printf(" hash collision with %08x\n", bd->next->addr); hash_collisions++; @@ -420,13 +402,19 @@ static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id) if (bd != NULL) block = bd->tcache_ptr; -#if (DRC_DEBUG & 1) +#if (DRC_DEBUG & 2) if (bd != NULL) bd->refcount++; #endif return block; } +static void *dr_failure(void) +{ + lprintf("recompilation failed\n"); + exit(1); +} + static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id) { #if LINK_BRANCHES @@ -459,7 +447,7 @@ static void dr_link_blocks(void *target, u32 pc, int tcache_id) for (i = 0; i < cnt; i++) { if (bl[i].target_pc == pc) { - dbg(1, "- link from %p", bl[i].jump); + dbg(2, "- link from %p", bl[i].jump); emith_jump_patch(bl[i].jump, target); // XXX: sync ARM caches (old jump should be fine)? } @@ -470,7 +458,7 @@ static void dr_link_blocks(void *target, u32 pc, int tcache_id) #define ADD_TO_ARRAY(array, count, item, failcode) \ array[count++] = item; \ if (count >= ARRAY_SIZE(array)) { \ - printf("warning: " #array " overflow\n"); \ + dbg(1, "warning: " #array " overflow"); \ failcode; \ } @@ -973,6 +961,10 @@ static int emit_memhandler_read_(int size, int ram_check) } } rcache_invalidate(); + + if (reg_map_g2h[SHR_SR] != -1) + emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4); + // assuming arg0 and retval reg matches return rcache_get_tmp_arg(0); } @@ -1030,6 +1022,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay) { int ctxr; host_arg2reg(ctxr, 2); + if (reg_map_g2h[SHR_SR] != -1) + emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4); + switch (size) { case 0: // 8 // XXX: consider inlining sh2_drc_write8 @@ -1055,6 +1050,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay) emith_call(sh2_drc_write32); break; } + + if (reg_map_g2h[SHR_SR] != -1) + emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4); rcache_invalidate(); } @@ -1122,13 +1120,15 @@ static void emit_do_static_regs(int is_write, int tmpr) static void emit_block_entry(void) { - int arg0, arg1, arg2; + int arg0; host_arg2reg(arg0, 0); + +#if (DRC_DEBUG & 8) || defined(PDB) + int arg1, arg2; host_arg2reg(arg1, 1); host_arg2reg(arg2, 2); -#if (DRC_DEBUG & 4) || defined(PDB) emit_do_static_regs(1, arg2); emith_move_r_r(arg1, CONTEXT_REG); emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ)); @@ -1164,12 +1164,6 @@ static void emit_block_entry(void) goto default_; \ } -#define FETCH_OP(pc) \ - dr_pc_base[(pc) / 2] - -#define FETCH32(a) \ - ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1]) - #define GET_Fx() \ ((op >> 4) & 0x0f) @@ -1182,9 +1176,7 @@ static void emit_block_entry(void) if (GET_Fx() >= n) \ goto default_ -// op_flags: data from 1st pass -#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2] -#define OF_DELAY_OP (1 << 0) +static void *dr_get_pc_base(u32 pc, int is_slave); static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) { @@ -1200,7 +1192,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) int literal_addr_count = 0; int pending_branch_cond = -1; int pending_branch_pc = 0; - u8 op_flags[BLOCK_CYCLE_LIMIT + 1]; + u8 op_flags[BLOCK_CYCLE_LIMIT]; struct { u32 delayed_op:2; u32 test_irq:1; @@ -1237,65 +1229,34 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) // predict tcache overflow tmp = tcache_ptr - tcache_bases[tcache_id]; if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) { - printf("tcache %d overflow\n", tcache_id); + dbg(1, "tcache %d overflow", tcache_id); return NULL; } block_entry = tcache_ptr; - dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', + dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', tcache_id, blkid_main, base_pc, block_entry); dr_link_blocks(tcache_ptr, base_pc, tcache_id); // 1st pass: scan forward for local branches - memset(op_flags, 0, sizeof(op_flags)); - for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) { - op = FETCH_OP(pc); - if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR - signed int offs = ((signed int)(op << 20) >> 19); - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,); - break; - } - if ((op & 0xf000) == 0) { - op &= 0xff; - if (op == 0x1b) // SLEEP - break; - if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - break; - } + scan_block(base_pc, sh2->is_slave, op_flags, &end_pc); + + // collect branch_targets that don't land on delay slots + for (pc = base_pc; pc <= end_pc; pc += 2) { + if (!(OP_FLAGS(pc) & OF_TARGET)) + continue; + if (OP_FLAGS(pc) & OF_DELAY_OP) { + OP_FLAGS(pc) &= ~OF_TARGET; continue; } - if ((op & 0xf0df) == 0x400b) { // JMP, JSR - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - break; - } - if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) - signed int offs = ((signed int)(op << 24) >> 23); - if (op & 0x0400) - OP_FLAGS(pc + 2) |= OF_DELAY_OP; - ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break); - } - if ((op & 0xff00) == 0xc300) // TRAPA - break; + ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break); } - end_pc = pc; - - // clean branch_targets that are not really local, - // and that land on delay slots - for (i = 0, tmp = 0; i < branch_target_count; i++) { - pc = branch_target_pc[i]; - if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP)) - branch_target_pc[tmp++] = branch_target_pc[i]; + if (branch_target_count > 0) { + memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); + memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count); } - branch_target_count = tmp; - memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); - memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count); // ------------------------------------------------- // 2nd pass: actual compilation @@ -1310,9 +1271,9 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) op = FETCH_OP(pc); - i = find_in_array(branch_target_pc, branch_target_count, pc); - if (i >= 0 || pc == base_pc) + if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc) { + i = find_in_array(branch_target_pc, branch_target_count, pc); if (pc != base_pc) { /* make "subblock" - just a mid-block entry */ @@ -1327,7 +1288,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_flush(); do_host_disasm(tcache_id); - dbg(1, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', + dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', tcache_id, branch_target_blkid[i], pc, tcache_ptr); subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]); @@ -1352,12 +1313,27 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_unlock_all(); } -#if (DRC_DEBUG & 3) - insns_compiled++; #if (DRC_DEBUG & 2) + insns_compiled++; +#endif +#if (DRC_DEBUG & 4) DasmSH2(sh2dasm_buff, pc, op); printf("%08x %04x %s\n", pc, op, sh2dasm_buff); #endif +#ifdef DRC_CMP + //if (out_pc != 0 && out_pc != (u32)-1) + // emit_move_r_imm32(SHR_PC, out_pc); + //else + if (!drcf.delayed_op) { + emit_move_r_imm32(SHR_PC, pc); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + FLUSH_CYCLES(sr); + // rcache_clean(); // FIXME + rcache_flush(); + emit_do_static_regs(1, 0); + emith_pass_arg_r(0, CONTEXT_REG); + emith_call(do_sh2_cmp); + } #endif pc += 2; @@ -1575,7 +1551,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) EMITH_JMP_END(DCOND_EQ); rcache_free_tmp(tmp); - cycles += 3; + cycles += 2; goto end_op; } goto default_; @@ -1698,8 +1674,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_clear_msb(tmp2, tmp3, 16); emith_mul(tmp, tmp, tmp2); rcache_free_tmp(tmp2); -// FIXME: causes timing issues in Doom? -// cycles++; goto end_op; } goto default_; @@ -1787,6 +1761,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); emith_mul_u64(tmp3, tmp4, tmp, tmp2); + cycles++; goto end_op; case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 @@ -1836,6 +1811,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); emith_mul_s64(tmp3, tmp4, tmp, tmp2); + cycles++; goto end_op; } goto default_; @@ -1861,6 +1837,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) sr = rcache_get_reg(SHR_SR, RC_GR_RMW); if (drcf.delayed_op) DELAY_SAVE_T(sr); +#ifndef DRC_CMP if (FETCH_OP(pc) == 0x8bfd) { // BF #-2 if (gconst_get(GET_Rn(), &tmp)) { // XXX: limit burned cycles @@ -1873,6 +1850,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_sh2_dtbf_loop(); goto end_op; } +#endif tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); emith_bic_r_imm(sr, T); emith_subf_r_imm(tmp, 1); @@ -1924,12 +1902,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) break; case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 tmp = SHR_SR; + cycles++; break; case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 tmp = SHR_GBR; + cycles++; break; case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 tmp = SHR_VBR; + cycles++; break; default: goto default_; @@ -2001,12 +1982,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) break; case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 tmp = SHR_SR; + cycles += 2; break; case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 tmp = SHR_GBR; + cycles += 2; break; case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 tmp = SHR_VBR; + cycles += 2; break; default: goto default_; @@ -2289,7 +2273,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) case 0x0d00: // BT/S label 10001101dddddddd case 0x0f00: // BF/S label 10001111dddddddd DELAYED_OP; - cycles--; // fallthrough case 0x0900: // BT label 10001001dddddddd case 0x0b00: // BF label 10001011dddddddd @@ -2297,7 +2280,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; i = ((signed int)(op << 24) >> 23); pending_branch_pc = pc + i + 2; - cycles += 2; goto end_op; } goto default_; @@ -2474,13 +2456,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) default_: elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", sh2->is_slave ? 's' : 'm', op, pc - 2); -#ifdef DRC_DEBUG_INTERP - emit_move_r_imm32(SHR_PC, pc - 2); - rcache_flush(); - emith_pass_arg_r(0, CONTEXT_REG); - emith_pass_arg_imm(1, op); - emith_call(sh2_do_op); -#endif break; } @@ -2491,17 +2466,20 @@ end_op: if (pending_branch_cond != -1 && drcf.delayed_op != 2) { u32 target_pc = pending_branch_pc; + int ctaken = drcf.delayed_op ? 1 : 2; void *target; sr = rcache_get_reg(SHR_SR, RC_GR_RMW); - // handle cycles FLUSH_CYCLES(sr); - rcache_clean(); if (drcf.use_saved_t) emith_tst_r_imm(sr, T_save); else emith_tst_r_imm(sr, T); + // handle cycles + emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12); + rcache_clean(); + #if LINK_BRANCHES if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) { // local branch @@ -2512,7 +2490,7 @@ end_op: branch_patch_count++; if (branch_patch_count == MAX_LOCAL_BRANCHES) { - printf("warning: too many local branches\n"); + dbg(1, "warning: too many local branches"); break; } } @@ -2578,8 +2556,8 @@ end_op: t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]); target = branch_target_ptr[t]; if (target == NULL) { - // flush pc and go back to dispatcher (should no longer happen) - printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr); + // flush pc and go back to dispatcher (this should no longer happen) + dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr); target = tcache_ptr; emit_move_r_imm32(SHR_PC, branch_patch_pc[i]); rcache_flush(); @@ -2623,7 +2601,6 @@ end_op: // mark literals for (i = 0; i < literal_addr_count; i++) { tmp = literal_addr[i]; - //printf("marking literal %08x\n", tmp); drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1; if (!(tmp & 3)) // assume long drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1; @@ -2635,12 +2612,12 @@ end_op: host_instructions_updated(block_entry, tcache_ptr); do_host_disasm(tcache_id); - dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", + dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", tcache_id, block_counts[tcache_id], tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM - dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); + dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); /* printf("~~~\n"); tcache_dsm_ptrs[tcache_id] = block_entry; @@ -2648,7 +2625,7 @@ end_op: printf("~~~\n"); */ -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) fflush(stdout); #endif @@ -2699,7 +2676,7 @@ static void sh2_generate_utils(void) emith_call(sh2_translate); emit_block_entry(); // XXX: can't translate, fail - emith_call(exit); + emith_call(dr_failure); // sh2_drc_test_irq(void) // assumes it's called from main function (may jump to dispatcher) @@ -2841,7 +2818,7 @@ static void sh2_generate_utils(void) MAKE_WRITE_WRAPPER(sh2_drc_write16); MAKE_WRITE_WRAPPER(sh2_drc_write16_slot); MAKE_WRITE_WRAPPER(sh2_drc_write32); -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) host_dasm_new_symbol(sh2_drc_read8); host_dasm_new_symbol(sh2_drc_read16); host_dasm_new_symbol(sh2_drc_read32); @@ -2850,7 +2827,7 @@ static void sh2_generate_utils(void) #endif rcache_invalidate(); -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) host_dasm_new_symbol(sh2_drc_entry); host_dasm_new_symbol(sh2_drc_dispatcher); host_dasm_new_symbol(sh2_drc_exit); @@ -2869,9 +2846,9 @@ static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id) void *tmp; // XXX: kill links somehow? - dbg(1, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]); + dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]); if (bd->addr == 0 || bd->tcache_ptr == NULL) { - printf(" killing dead block!? %08x\n", bd->addr); + dbg(1, " killing dead block!? %08x", bd->addr); return bd->tcache_ptr; } @@ -2917,7 +2894,7 @@ static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, break; if (!(*p & 1)) { - printf("smc rm: missing block start for %08x?\n", a); + dbg(1, "smc rm: missing block start for %08x?", a); p = pt; } @@ -2950,27 +2927,25 @@ static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) { - dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); + dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff); } void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) { - dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); + dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid], 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff); } -void sh2_execute(SH2 *sh2c, int cycles) +int sh2_execute(SH2 *sh2c, int cycles) { int ret_cycles; - sh2 = sh2c; // XXX - sh2c->cycles_aim += cycles; - cycles = sh2c->cycles_aim - sh2c->cycles_done; + sh2c->cycles_timeslice = cycles; // cycles are kept in SHR_SR unused bits (upper 20) - // bit19 contains T saved for delay slot + // bit11 contains T saved for delay slot // others are usual SH2 flags sh2c->sr &= 0x3f3; sh2c->sr |= cycles << 12; @@ -2979,12 +2954,12 @@ void sh2_execute(SH2 *sh2c, int cycles) // TODO: irq cycles ret_cycles = (signed int)sh2c->sr >> 12; if (ret_cycles > 0) - printf("warning: drc returned with cycles: %d\n", ret_cycles); + dbg(1, "warning: drc returned with cycles: %d", ret_cycles); - sh2c->cycles_done += cycles - ret_cycles; + return sh2c->cycles_timeslice - ret_cycles; } -#if (DRC_DEBUG & 1) +#if (DRC_DEBUG & 2) void block_stats(void) { int c, b, i, total = 0; @@ -3069,7 +3044,7 @@ int sh2_drc_init(SH2 *sh2) // tmp PicoOpt |= POPT_DIS_VDP_FIFO; -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) for (i = 0; i < ARRAY_SIZE(block_tables); i++) tcache_dsm_ptrs[i] = tcache_bases[i]; // disasm the utils @@ -3102,7 +3077,7 @@ void sh2_drc_finish(SH2 *sh2) block_stats(); for (i = 0; i < TCACHE_BUFFERS; i++) { -#if (DRC_DEBUG & 2) +#if (DRC_DEBUG & 4) printf("~~~ tcache %d\n", i); tcache_dsm_ptrs[i] = tcache_bases[i]; tcache_ptr = tcache_ptrs[i]; @@ -3125,3 +3100,91 @@ void sh2_drc_finish(SH2 *sh2) hash_table = NULL; } } + +#endif /* DRC_SH2 */ + +static void *dr_get_pc_base(u32 pc, int is_slave) +{ + void *ret = NULL; + u32 mask = 0; + + if ((pc & ~0x7ff) == 0) { + // BIOS + ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; + mask = 0x7ff; + } + else if ((pc & 0xfffff000) == 0xc0000000) { + // data array + ret = Pico32xMem->data_array[is_slave]; + mask = 0xfff; + } + else if ((pc & 0xc6000000) == 0x06000000) { + // SDRAM + ret = Pico32xMem->sdram; + mask = 0x03ffff; + } + else if ((pc & 0xc6000000) == 0x02000000) { + // ROM + ret = Pico.rom; + mask = 0x3fffff; + } + + if (ret == NULL) + return (void *)-1; // NULL is valid value + + return (char *)ret - (pc & ~mask); +} + +void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc) +{ + u16 *dr_pc_base; + u32 pc, target, op; + int cycles; + + memset(op_flags, 0, BLOCK_CYCLE_LIMIT); + + dr_pc_base = dr_get_pc_base(base_pc, is_slave); + + for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) { + op = FETCH_OP(pc); + if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR + signed int offs = ((signed int)(op << 20) >> 19); + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + target = pc + offs + 2; + if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2) + OP_FLAGS(target) |= OF_TARGET; + break; + } + if ((op & 0xf000) == 0) { + op &= 0xff; + if (op == 0x1b) // SLEEP + break; + // BRAF, BSRF, RTS, RTE + if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + continue; + } + if ((op & 0xf0df) == 0x400b) { // JMP, JSR + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) + signed int offs = ((signed int)(op << 24) >> 23); + if (op & 0x0400) + OP_FLAGS(pc + 2) |= OF_DELAY_OP; + target = pc + offs + 4; + if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2) + OP_FLAGS(target) |= OF_TARGET; + } + if ((op & 0xff00) == 0xc300) // TRAPA + break; + } + *end_pc = pc; +} + +// vim:shiftwidth=2:ts=2:expandtab