X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=pico%2F32x%2F32x.c;h=ab522e41a6d6840d16175e61ff5ad9d1dbd1475a;hb=a76fad41291b7be0b42554353d6775dcdff065e0;hp=0d56b9827fca3627fb2af77cdc5d96658523ea8c;hpb=5ac99d9adf88799fd2de3ec787409ed1f2255168;p=picodrive.git

diff --git a/pico/32x/32x.c b/pico/32x/32x.c
index 0d56b98..ab522e4 100644
--- a/pico/32x/32x.c
+++ b/pico/32x/32x.c
@@ -39,13 +39,13 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
     m68k_cycles = sh2_cycles_done_m68k(active_sh2);
 
   // msh2
-  irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
+  irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
   while ((irqs >>= 1))
     mlvl++;
   mlvl *= 2;
 
   // ssh2
-  irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
+  irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
   while ((irqs >>= 1))
     slvl++;
   slvl *= 2;
@@ -67,6 +67,33 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
   elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
 }
 
+// the mask register is inconsistent, CMD is supposed to be a mask,
+// while others are actually irq trigger enables?
+// TODO: test on hw..
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
+{
+  Pico32x.sh2irqs |= mask & P32XI_VRES;
+  Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
+  Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
+
+  p32x_update_irls(sh2, m68k_cycles);
+}
+
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
+{
+  if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
+    Pico32x.sh2irqi[0] |= P32XI_CMD;
+  else
+    Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+
+  if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
+    Pico32x.sh2irqi[1] |= P32XI_CMD;
+  else
+    Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+
+  p32x_update_irls(sh2, m68k_cycles);
+}
+
 void Pico32xStartup(void)
 {
   elprintf(EL_STATUS|EL_32X, "32X startup");
@@ -174,8 +201,7 @@ void PicoReset32x(void)
 {
   if (PicoAHW & PAHW_32X) {
     msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
-    Pico32x.sh2irqs |= P32XI_VRES;
-    p32x_update_irls(NULL, SekCyclesDoneT2());
+    p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES);
     p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
     p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
     p32x_pwm_ctl_changed();
@@ -222,8 +248,7 @@ static void p32x_start_blank(void)
     Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
   }
 
-  Pico32x.sh2irqs |= P32XI_VINT;
-  p32x_update_irls(NULL, SekCyclesDoneT2());
+  p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT);
   p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
   p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
 }
@@ -265,8 +290,7 @@ static void fillend_event(unsigned int now)
 
 static void hint_event(unsigned int now)
 {
-  Pico32x.sh2irqs |= P32XI_HINT;
-  p32x_update_irls(NULL, now);
+  p32x_trigger_irq(NULL, now, P32XI_HINT);
   p32x_schedule_hint(NULL, now);
 }
 
@@ -499,6 +523,8 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
 
 #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
   SekRunM68k(m68k_cycles); \
+  if (Pico32x.emu_flags & P32XF_Z80_32X_IO) \
+    PicoSyncZ80(SekCycleCnt); \
   if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
     p32x_sync_sh2s(SekCyclesDoneT2()); \
 } while (0)