X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;ds=sidebyside;f=pico%2F32x%2Fmemory.c;h=2eaa5b8e24664dde8c5893b5a626ac38b9823edc;hb=236990cf7712bf4c2b46d06842c4f5f037e83328;hp=00b41a0e622e5c8998cfa4797bb60c309f1dcfb4;hpb=be20816c4c487c4b114aa444b1a5819d5785b118;p=picodrive.git diff --git a/pico/32x/memory.c b/pico/32x/memory.c index 00b41a0..2eaa5b8 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -1,6 +1,13 @@ #include "../pico_int.h" #include "../memory.h" +#if 0 +#undef ash2_end_run +#undef SekEndRun +#define ash2_end_run(x) +#define SekEndRun(x) +#endif + static const char str_mars[] = "MARS"; struct Pico32xMem *Pico32xMem; @@ -35,9 +42,10 @@ static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp) Pico32x.emu_flags |= flag; } } - else + else { pd->cnt = 0; - pd->addr = a; + pd->addr = a; + } pd->cycles = cycles; return ret; @@ -114,6 +122,10 @@ static void dma_68k2sh2_do(void) if (dmac0->tcr0 != *dreqlen) elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen); + // HACK: assume bus is busy and SH2 is halted + // XXX: use different mechanism for this, not poll det + Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL; + for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) { extern void p32x_sh2_write16(u32 a, u32 d, int id); elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen); @@ -147,7 +159,7 @@ static u32 p32x_reg_read16(u32 a) return sh2_comm_faker(a); #else if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) { - SekEndRun(16); + SekEndTimeslice(16); } #endif @@ -177,7 +189,7 @@ static void p32x_reg_write8(u32 a, u32 d) switch (a) { case 0: // adapter ctl r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM); - break; + return; case 3: // irq ctl if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) { Pico32x.sh2irqi[0] |= P32XI_CMD; @@ -189,20 +201,31 @@ static void p32x_reg_write8(u32 a, u32 d) p32x_update_irls(); SekEndRun(16); } - break; + return; case 5: // bank d &= 7; if (r[4 / 2] != d) { r[4 / 2] = d; bank_switch(d); } - break; + return; case 7: // DREQ ctl r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); - break; + return; case 0x1b: // TV r[0x1a / 2] = d; - break; + return; + } + + if ((a & 0x30) == 0x20) { + u8 *r8 = (u8 *)r; + r8[a ^ 1] = d; + p32x_poll_undetect(&sh2_poll[0], 0); + p32x_poll_undetect(&sh2_poll[1], 0); + // if some SH2 is busy waiting, it needs to see the result ASAP + if (SekCyclesLeftNoMCD > 32) + SekEndRun(32); + return; } } @@ -244,9 +267,11 @@ static void p32x_reg_write16(u32 a, u32 d) // comm port else if ((a & 0x30) == 0x20 && r[a / 2] != d) { r[a / 2] = d; - if (p32x_poll_undetect(&sh2_poll[0], 0) || p32x_poll_undetect(&sh2_poll[1], 0)) - // if some SH2 is busy waiting, it needs to see the result ASAP - SekEndRun(16); + p32x_poll_undetect(&sh2_poll[0], 0); + p32x_poll_undetect(&sh2_poll[1], 0); + // same as for w8 + if (SekCyclesLeftNoMCD > 32) + SekEndRun(32); return; } // PWM @@ -310,7 +335,7 @@ static void p32x_vdp_write16(u32 a, u32 d) } if (a == 8) { // fill data u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; - int len = Pico32x.vdp_regs[4 / 2]; + int len = Pico32x.vdp_regs[4 / 2] + 1; a = Pico32x.vdp_regs[6 / 2]; while (len--) { dram[a] = d; @@ -335,7 +360,9 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid) switch (a) { case 0x00: // adapter/irq ctl return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; - case 0x04: // H count + case 0x04: // H count (often as comm too) + if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0)) + ash2_end_run(8); return Pico32x.sh2_regs[4 / 2]; case 0x10: // DREQ len return r[a / 2]; @@ -365,16 +392,25 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) case 0: // FM Pico32x.regs[0] &= ~P32XS_FM; Pico32x.regs[0] |= (d << 8) & P32XS_FM; - break; + return; case 1: // Pico32x.sh2irq_mask[cpuid] = d & 0x8f; Pico32x.sh2_regs[0] &= ~0x80; Pico32x.sh2_regs[0] |= d & 0x80; p32x_update_irls(); - break; + return; case 5: // H count Pico32x.sh2_regs[4 / 2] = d & 0xff; - break; + p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); + return; + } + + if ((a & 0x30) == 0x20) { + u8 *r8 = (u8 *)Pico32x.regs; + r8[a ^ 1] = d; + p32x_poll_undetect(&m68k_poll, 0); + p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0); + return; } } @@ -488,10 +524,8 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id) dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id)); dmac0->tcr0 &= 0xffffff; - // HACK: assume bus is busy and SH2 is halted - // XXX: use different mechanism for this, not poll det - Pico32x.emu_flags |= id ? P32XF_SSH2POLL : P32XF_MSH2POLL; - ash2_end_run(5); + // HACK: assume 68k starts writing soon and end the timeslice + ash2_end_run(16); // DREQ is only sent after first 4 words are written. // we do multiple of 4 words to avoid messing up alignment @@ -711,7 +745,8 @@ u32 p32x_sh2_read8(u32 a, int id) if ((a & ~0xfff) == 0xc0000000) return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; - if ((a & 0xdffe0000) == 0x04000000) { + if ((a & 0xdffc0000) == 0x04000000) { + /* XXX: overwrite readable as normal? */ u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; return dram[(a & 0x1ffff) ^ 1]; } @@ -775,6 +810,8 @@ u32 p32x_sh2_read16(u32 a, int id) if ((a & 0xdfffff00) == 0x4000) { d = p32x_sh2reg_read16(a, id); + if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM + return d; goto out; } @@ -825,8 +862,8 @@ void p32x_sh2_write8(u32 a, u32 d, int id) if (!(a & 0x20000) || d) { dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; dram[(a & 0x1ffff) ^ 1] = d; - return; } + return; } if ((a & ~0xfff) == 0xc0000000) { @@ -855,7 +892,7 @@ void p32x_sh2_write8(u32 a, u32 d, int id) void p32x_sh2_write16(u32 a, u32 d, int id) { - if ((a & 0xdffffc00) == 0x4000) + if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));