X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Cyclone%2FCyclone.h;h=c2c27d8d0d654948e95b1439fd84441cd4361815;hb=d9d77995ec88700f438b3638df179a014bf4f6b3;hp=77ea26889975d7bc24ca52c376ceed65d4154e5c;hpb=c41b9b971773b8f4e20fa07f1570fe7aec941bcd;p=cyclone68000.git

diff --git a/Cyclone/Cyclone.h b/Cyclone/Cyclone.h
index 77ea268..c2c27d8 100644
--- a/Cyclone/Cyclone.h
+++ b/Cyclone/Cyclone.h
@@ -1,13 +1,18 @@
 
 // Cyclone 68000 Emulator - Header File
 
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)
 
 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
 // You can choose the license that has the most advantages for you.
 
 // SVN repository can be found at http://code.google.com/p/cyclone68000/
 
+
+#ifndef __CYCLONE_H__
+#define __CYCLONE_H__
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -16,32 +21,79 @@ extern int CycloneVer; // Version number of library
 
 struct Cyclone
 {
-  unsigned int d[8];   // [r7,#0x00]
-  unsigned int a[8];   // [r7,#0x20]
-  unsigned int pc;     // [r7,#0x40] Memory Base+PC
-  unsigned char srh;   // [r7,#0x44] Status Register high (T_S__III)
-  unsigned char xc;    // [r7,#0x45] Extend flag (____??X?)
-  unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV)
-  unsigned char irq;   // [r7,#0x47] IRQ level
-  unsigned int osp;    // [r7,#0x48] Other Stack Pointer (USP/SSP)
-  unsigned int vector; // [r7,#0x50] IRQ vector (temporary)
-  int pad1[3];
-  int cycles;          // [r7,#0x5c]
-  int membase;         // [r7,#0x60] Memory Base (ARM address minus 68000 address)
-  unsigned int   (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc
-  unsigned char  (*read8  )(unsigned int a);  // [r7,#0x68]
-  unsigned short (*read16 )(unsigned int a);  // [r7,#0x6c]
-  unsigned int   (*read32 )(unsigned int a);  // [r7,#0x70]
+  unsigned int d[8];    // [r7,#0x00]
+  unsigned int a[8];    // [r7,#0x20]
+  unsigned int pc;      // [r7,#0x40] Memory Base (.membase) + 68k PC
+  unsigned char srh;    // [r7,#0x44] Status Register high (T_S__III)
+  unsigned char unused; // [r7,#0x45] Unused
+  unsigned char flags;  // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]
+  unsigned char irq;    // [r7,#0x47] IRQ level
+  unsigned int osp;     // [r7,#0x48] Other Stack Pointer (USP/SSP)
+  unsigned int xc;      // [r7,#0x4c] Extend flag (bit29: ??X? _)
+  unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)
+  unsigned int jumptab; // [r7,#0x54] Jump table pointer
+  int state_flags;      // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt
+  int cycles;           // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()
+  int membase;          // [r7,#0x60] Memory Base (ARM address minus 68000 address)
+  unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc
+  unsigned int (*read8  )(unsigned int a);  // [r7,#0x68]
+  unsigned int (*read16 )(unsigned int a);  // [r7,#0x6c]
+  unsigned int (*read32 )(unsigned int a);  // [r7,#0x70]
   void (*write8 )(unsigned int a,unsigned char  d); // [r7,#0x74]
   void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]
   void (*write32)(unsigned int a,unsigned int   d); // [r7,#0x7c]
-  unsigned char  (*fetch8 )(unsigned int a);  // [r7,#0x80]
-  unsigned short (*fetch16)(unsigned int a);  // [r7,#0x84]
-  unsigned int   (*fetch32)(unsigned int a);  // [r7,#0x88]
+  unsigned int (*fetch8 )(unsigned int a);  // [r7,#0x80]
+  unsigned int (*fetch16)(unsigned int a);  // [r7,#0x84]
+  unsigned int (*fetch32)(unsigned int a);  // [r7,#0x88]
+  int  (*IrqCallback)(int int_level);       // [r7,#0x8c] optional irq callback function, see config.h
+  void (*ResetCallback)(void);              // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.
+  int  (*UnrecognizedCallback)(void);       // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.
+  unsigned int internal[6];                 // [r7,#0x98] reserved for internal use, do not change.
 };
 
+// Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h
+void CycloneInit(void);
+
+// Reset
+void CycloneReset(struct Cyclone *pcy);
+
+// Run cyclone. Cycles should be specified in context (pcy->cycles)
 void CycloneRun(struct Cyclone *pcy);
 
+// Utility functions to get and set SR
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);
+unsigned int CycloneGetSr(const struct Cyclone *pcy);
+
+// Generates irq exception if needed (if pcy->irq > mask).
+// Returns cycles used for exception if it was generated, 0 otherwise.
+int CycloneFlushIrq(struct Cyclone *pcy);
+
+// Functions for saving and restoring state.
+// CycloneUnpack() uses checkpc(), so it must be initialized.
+// save_buffer must point to buffer of 128 (0x80) bytes of size.
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);
+
+// genesis: if 1, switch to normal TAS handlers
+void CycloneSetRealTAS(int use_real);
+
+
+// These values are special return values for IrqCallback.
+
+// Causes an interrupt autovector (0x18 + interrupt level) to be taken.
+// This happens in a real 68K if VPA or AVEC is asserted during an interrupt
+// acknowledge cycle instead of DTACK (the most common situation).
+#define CYCLONE_INT_ACK_AUTOVECTOR    -1
+
+// Causes the spurious interrupt vector (0x18) to be taken
+// This happens in a real 68K if BERR is asserted during the interrupt
+// acknowledge cycle (i.e. no devices responded to the acknowledge).
+#define CYCLONE_INT_ACK_SPURIOUS      -2
+
+
 #ifdef __cplusplus
 } // End of extern "C"
 #endif
+
+#endif // __CYCLONE_H__
+