X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2FMemory.c;h=21db15e481bce97052599602f0026d783b831163;hb=a67855765d6106f3fd8737ec35c2165460d2705f;hp=c9c9a020cc0f9a000f930bc9d56934b13478f3a0;hpb=fa1e5e2948e9b06dec3353081081173f7ae4d742;p=picodrive.git diff --git a/Pico/Memory.c b/Pico/Memory.c index c9c9a02..21db15e 100644 --- a/Pico/Memory.c +++ b/Pico/Memory.c @@ -70,6 +70,8 @@ static u32 CPU_CALL PicoCheckPc(u32 pc) #if defined(EMU_C68K) pc-=PicoCpu.membase; // Get real pc pc&=0xfffffe; + if (pc == 0) + return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off PicoCpu.membase=PicoMemBase(pc); @@ -192,6 +194,7 @@ static void OtherWrite8End(u32 a,u32 d,int realsize) //if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone()); //if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT()); if(a >= SRam.start && a <= SRam.end) { + dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc); unsigned int sreg = Pico.m.sram_reg; if(!(sreg & 0x10)) { // not detected SRAM @@ -229,7 +232,9 @@ static void OtherWrite8End(u32 a,u32 d,int realsize) #else // sram access register if(a == 0xA130F1) { - Pico.m.sram_reg = (u8)(d&3); + dprintf("sram reg=%02x", d); + Pico.m.sram_reg &= ~3; + Pico.m.sram_reg |= (u8)(d&3); return; } #endif @@ -392,16 +397,13 @@ static void CPU_CALL PicoWrite8(u32 a,u8 d) //if ((a&0xe0ffff)==0xe0a9ba+0x69c) // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc); - - if ((a&0xe00000)==0xe00000) { - if((a&0xffff)==0xf62a) dprintf("(f62a) = %02x [%i|%i] @ %x", d, Pico.m.scanline, SekCyclesDone(), SekPc); - u8 *pm=(u8 *)(Pico.ram+((a^1)&0xffff)); pm[0]=d; return; } // Ram + if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram a&=0xffffff; OtherWrite8(a,d,8); } -static void CPU_CALL PicoWrite16(u32 a,u16 d) +void CPU_CALL PicoWrite16(u32 a,u16 d) { #ifdef __debug_io dprintf("w16: %06x, %04x", a&0xffffff, d);