X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2FMemory.c;h=aa15bef39ff40832cad8874c2a005d96ef844409;hb=7d4906bfc93ced40a544534f433f06b00add52b0;hp=01e92f4a328adb416b8cd8d961ede48592f4afc0;hpb=eff55556cff77fd64cff4be32e449e0a58aed6fe;p=picodrive.git

diff --git a/Pico/Memory.c b/Pico/Memory.c
index 01e92f4..aa15bef 100644
--- a/Pico/Memory.c
+++ b/Pico/Memory.c
@@ -26,6 +26,7 @@ extern unsigned int lastSSRamWrite; // used by serial SRAM code
 #ifdef _ASM_MEMORY_C
 u32  PicoRead8(u32 a);
 u32  PicoRead16(u32 a);
+void PicoWrite8(u32 a,u8 d);
 void PicoWriteRomHW_SSF2(u32 a,u32 d);
 void PicoWriteRomHW_in1 (u32 a,u32 d);
 #endif
@@ -38,6 +39,12 @@ int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
 extern unsigned int ppop;
 #endif
 
+#ifdef IO_STATS
+void log_io(unsigned int addr, int bits, int rw);
+#else
+#define log_io(...)
+#endif
+
 #if defined(EMU_C68K) || defined(EMU_A68K)
 static __inline int PicoMemBase(u32 pc)
 {
@@ -74,7 +81,10 @@ static u32 CPU_CALL PicoCheckPc(u32 pc)
 //  pc&=0xfffffe;
   pc&=~1;
   if ((pc<<8) == 0)
+  {
+    printf("%i:%03i: game crash detected @ %06x\n", Pico.m.frame_count, Pico.m.scanline, SekPc);
     return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off
+  }
 
   PicoCpu.membase=PicoMemBase(pc&0x00ffffff);
   PicoCpu.membase-=pc&0xff000000;
@@ -104,15 +114,89 @@ PICO_INTERNAL_ASM void PicoMemReset(void)
 
 // -----------------------------------------------------------------
 
-#ifndef _ASM_MEMORY_C
-// address must already be checked
-static int SRAMRead(u32 a)
+int PadRead(int i)
 {
-  u8 *d = SRam.data-SRam.start+a;
-  return (d[0]<<8)|d[1];
+  int pad,value,data_reg;
+  pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
+  data_reg=Pico.ioports[i+1];
+
+  // orr the bits, which are set as output
+  value = data_reg&(Pico.ioports[i+4]|0x80);
+
+  if(PicoOpt & 0x20) { // 6 button gamepad enabled
+    int phase = Pico.m.padTHPhase[i];
+
+    if(phase == 2 && !(data_reg&0x40)) { // TH
+      value|=(pad&0xc0)>>2;              // ?0SA 0000
+      return value;
+    } else if(phase == 3) {
+      if(data_reg&0x40)
+        value|=(pad&0x30)|((pad>>8)&0xf);  // ?1CB MXYZ
+      else
+        value|=((pad&0xc0)>>2)|0x0f;       // ?0SA 1111
+      return value;
+    }
+  }
+
+  if(data_reg&0x40) // TH
+       value|=(pad&0x3f);              // ?1CB RLDU
+  else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
+
+  return value; // will mirror later
 }
+
+
+#ifndef _ASM_MEMORY_C
+static
 #endif
+u32 SRAMRead(u32 a)
+{
+  unsigned int sreg = Pico.m.sram_reg;
+  if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM
+    elprintf(EL_SRAMIO, "normal sram detected.");
+    Pico.m.sram_reg|=0x10; // should be normal SRAM
+  }
+  if(sreg & 4) // EEPROM read
+    return SRAMReadEEPROM();
+  else // if(sreg & 1) // (sreg&5) is one of prerequisites
+    return *(u8 *)(SRam.data-SRam.start+a);
+}
 
+static void SRAMWrite(u32 a, u32 d)
+{
+  unsigned int sreg = Pico.m.sram_reg;
+  if(!(sreg & 0x10)) {
+    // not detected SRAM
+    if((a&~1)==0x200000) {
+      elprintf(EL_SRAMIO, "eeprom detected.");
+      sreg|=4; // this should be a game with EEPROM (like NBA Jam)
+      SRam.start=0x200000; SRam.end=SRam.start+1;
+    } else
+      elprintf(EL_SRAMIO, "normal sram detected.");
+    sreg|=0x10;
+    Pico.m.sram_reg=sreg;
+  }
+  if(sreg & 4) { // EEPROM write
+    // this diff must be at most 16 for NBA Jam to work
+    if(SekCyclesDoneT()-lastSSRamWrite < 16) {
+      // just update pending state
+      elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);
+      SRAMUpdPending(a, d);
+    } else {
+      int old=sreg;
+      SRAMWriteEEPROM(sreg>>6); // execute pending
+      SRAMUpdPending(a, d);
+      if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed
+        lastSSRamWrite = SekCyclesDoneT();
+    }
+  } else if(!(sreg & 2)) {
+    u8 *pm=(u8 *)(SRam.data-SRam.start+a);
+    if(*pm != (u8)d) {
+      SRam.changed = 1;
+      *pm=(u8)d;
+    }
+  }
+}
 
 // for nonstandard reads
 #ifndef _ASM_MEMORY_C
@@ -122,8 +206,6 @@ u32 OtherRead16End(u32 a, int realsize)
 {
   u32 d=0;
 
-  dprintf("strange r%i: %06x @%06x", realsize, a&0xffffff, SekPc);
-
   // for games with simple protection devices, discovered by Haze
   // some dumb detection is used, but that should be enough to make things work
   if ((a>>22) == 1 && Pico.romsize >= 512*1024) {
@@ -185,7 +267,7 @@ u32 OtherRead16End(u32 a, int realsize)
   }
 
 end:
-  dprintf("ret = %04x", d);
+  elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc);
   return d;
 }
 
@@ -195,35 +277,9 @@ end:
 static void OtherWrite8End(u32 a,u32 d,int realsize)
 {
   // sram
-  //if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());
-  //if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());
   if(a >= SRam.start && a <= SRam.end) {
-    dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
-    unsigned int sreg = Pico.m.sram_reg;
-    if(!(sreg & 0x10)) {
-      // not detected SRAM
-      if((a&~1)==0x200000) {
-        Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)
-        SRam.start=0x200000; SRam.end=SRam.start+1;
-      }
-      Pico.m.sram_reg|=0x10;
-    }
-    if(sreg & 4) { // EEPROM write
-      if(SekCyclesDoneT()-lastSSRamWrite < 46) {
-        // just update pending state
-        SRAMUpdPending(a, d);
-      } else {
-        SRAMWriteEEPROM(sreg>>6); // execute pending
-        SRAMUpdPending(a, d);
-        lastSSRamWrite = SekCyclesDoneT();
-      }
-    } else if(!(sreg & 2)) {
-      u8 *pm=(u8 *)(SRam.data-SRam.start+a);
-      if(*pm != (u8)d) {
-        SRam.changed = 1;
-        *pm=(u8)d;
-      }
-    }
+    elprintf(EL_SRAMIO, "sram w8  [%06x] %02x @ %06x", a, d, SekPc);
+    SRAMWrite(a, d);
     return;
   }
 
@@ -236,13 +292,13 @@ static void OtherWrite8End(u32 a,u32 d,int realsize)
 #else
   // sram access register
   if(a == 0xA130F1) {
-    dprintf("sram reg=%02x", d);
+    elprintf(EL_SRAMIO, "sram reg=%02x", d);
     Pico.m.sram_reg &= ~3;
     Pico.m.sram_reg |= (u8)(d&3);
     return;
   }
 #endif
-  dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
+  elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
 
   if(a >= 0xA13004 && a < 0xA13040) {
     // dumb 12-in-1 or 4-in-1 banking support
@@ -278,35 +334,20 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a)
 
 #if !(defined(EMU_C68K) && defined(EMU_M68K))
   // sram
-  if(a >= SRam.start && a <= SRam.end) {
-    unsigned int sreg = Pico.m.sram_reg;
-    if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM
-      Pico.m.sram_reg|=0x10; // should be normal SRAM
-    }
-    if(sreg & 4) { // EEPROM read
-      d = SRAMReadEEPROM();
-      goto end;
-    } else if(sreg & 1) {
-      d = *(u8 *)(SRam.data-SRam.start+a);
-      goto end;
-    }
+  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
+    d = SRAMRead(a);
+    elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
+    goto end;
   }
 #endif
 
   if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom
+  log_io(a, 8, 0);
   if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
 
   d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8;
 
-  end:
-
-  //if ((a&0xe0ffff)==0xe0AE57+0x69c)
-  //  dprintf("r8 : %06x,   %02x @%06x", a&0xffffff, (u8)d, SekPc);
-  //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
-  //  dprintf("r8 : %06x,   %02x @%06x", a&0xffffff, d, SekPc);
-
-  //if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());
-  //dprintf("r8 : %06x,   %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);
+end:
 #ifdef __debug_io
   dprintf("r8 : %06x,   %02x @%06x", a&0xffffff, (u8)d, SekPc);
 #endif
@@ -329,20 +370,20 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a)
 
 #if !(defined(EMU_C68K) && defined(EMU_M68K))
   // sram
-  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {
+  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
     d = SRAMRead(a);
+    d |= d<<8;
+    elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
     goto end;
   }
 #endif
 
   if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom
+  log_io(a, 16, 0);
 
   d = OtherRead16(a, 16);
 
-  end:
-  //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)
-  //  dprintf("r16: %06x, %04x  @%06x", a&0xffffff, d, SekPc);
-
+end:
 #ifdef __debug_io
   dprintf("r16: %06x, %04x  @%06x", a&0xffffff, d, SekPc);
 #endif
@@ -364,16 +405,19 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)
   a&=0xfffffe;
 
   // sram
-  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {
+  if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
     d = (SRAMRead(a)<<16)|SRAMRead(a+2);
+    d |= d<<8;
+    elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);
     goto end;
   }
 
   if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom
+  log_io(a, 32, 0);
 
   d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
 
-  end:
+end:
 #ifdef __debug_io
   dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
 #endif
@@ -390,7 +434,8 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)
 // -----------------------------------------------------------------
 //                            Write Ram
 
-static void CPU_CALL PicoWrite8(u32 a,u8 d)
+#ifndef _ASM_MEMORY_C
+PICO_INTERNAL_ASM void CPU_CALL PicoWrite8(u32 a,u8 d)
 {
 #ifdef __debug_io
   dprintf("w8 : %06x,   %02x @%06x", a&0xffffff, d, SekPc);
@@ -399,13 +444,16 @@ static void CPU_CALL PicoWrite8(u32 a,u8 d)
   lastwrite_cyc_d[lwp_cyc++&15] = d;
 #endif
   //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
+  //if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());
   //  dprintf("w8 : %06x,   %02x @%06x", a&0xffffff, d, SekPc);
 
   if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram
+  log_io(a, 8, 1);
 
   a&=0xffffff;
-  OtherWrite8(a,d,8);
+  OtherWrite8(a,d);
 }
+#endif
 
 void CPU_CALL PicoWrite16(u32 a,u16 d)
 {
@@ -415,10 +463,9 @@ void CPU_CALL PicoWrite16(u32 a,u16 d)
 #if defined(EMU_C68K) && defined(EMU_M68K)
   lastwrite_cyc_d[lwp_cyc++&15] = d;
 #endif
-  //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)
-  //  dprintf("w16: %06x, %04x  @%06x", a&0xffffff, d, SekPc);
 
   if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram
+  log_io(a, 16, 1);
 
   a&=0xfffffe;
   OtherWrite16(a,d);
@@ -440,6 +487,7 @@ static void CPU_CALL PicoWrite32(u32 a,u32 d)
     pm[0]=(u16)(d>>16); pm[1]=(u16)d;
     return;
   }
+  log_io(a, 32, 1);
 
   a&=0xfffffe;
   OtherWrite16(a,  (u16)(d>>16));
@@ -589,14 +637,17 @@ void PicoWriteCD8w (unsigned int a, unsigned char d);
 void PicoWriteCD16w(unsigned int a, unsigned short d);
 void PicoWriteCD32w(unsigned int a, unsigned int d);
 
+/* it appears that Musashi doesn't always mask the unused bits */
 unsigned int  m68k_read_memory_8(unsigned int address)
 {
-    return (PicoMCD&1) ? PicoReadCD8w(address)  : PicoRead8(address);
+    unsigned int d = (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);
+    return d&0xff;
 }
 
 unsigned int  m68k_read_memory_16(unsigned int address)
 {
-    return (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);
+    unsigned int d = (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);
+    return d&0xffff;
 }
 
 unsigned int  m68k_read_memory_32(unsigned int address)
@@ -642,13 +693,15 @@ PICO_INTERNAL unsigned char z80_read(unsigned short a)
     addr68k+=a&0x7fff;
 
     ret = (u8) PicoRead8(addr68k);
-    //dprintf("z80->68k w8 : %06x,   %02x", addr68k, ret);
+    elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
     goto end;
   }
 
   // should not be needed || dprintf("z80_read RAM");
   if (a<0x4000) { ret = (u8) Pico.zram[a&0x1fff]; goto end; }
 
+  elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret);
+
 end:
   return ret;
 }
@@ -667,7 +720,7 @@ PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a)
 
   if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)
   {
-    if(PicoOpt&1) emustatus|=YM2612Write(a, data);
+    if(PicoOpt&1) emustatus|=YM2612Write(a, data) & 1;
     return;
   }
 
@@ -690,13 +743,15 @@ PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a)
     u32 addr68k;
     addr68k=Pico.m.z80_bank68k<<15;
     addr68k+=a&0x7fff;
+    elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
     PicoWrite8(addr68k, data);
-    //dprintf("z80->68k w8 : %06x,   %02x", addr68k, data);
     return;
   }
 
   // should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr);
   if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }
+
+  elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
 }
 
 PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)