X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2FMemory.c;h=dbf0118a9c99ee4083ef952a5a3ee7c21d20f926;hb=e5fa9817777032758511868c8aaa9ff780786c3f;hp=ec31ea25e65753e7cb336bd1f86f5abdc2aebcce;hpb=4f65685b9708aa567f407fd8e0a42c6a7ff85673;p=picodrive.git diff --git a/Pico/Memory.c b/Pico/Memory.c index ec31ea2..dbf0118 100644 --- a/Pico/Memory.c +++ b/Pico/Memory.c @@ -1,14 +1,12 @@ // This is part of Pico Library // (c) Copyright 2004 Dave, All rights reserved. -// (c) Copyright 2006 notaz, All rights reserved. +// (c) Copyright 2006,2007 notaz, All rights reserved. // Free for non-commercial use. // For commercial use, separate licencing terms must be obtained. -#define __debug_io - #include "PicoInt.h" #include "sound/ym2612.h" @@ -26,13 +24,12 @@ extern unsigned int lastSSRamWrite; // used by serial SRAM code #ifdef _ASM_MEMORY_C u32 PicoRead8(u32 a); u32 PicoRead16(u32 a); +void PicoWrite8(u32 a,u8 d); void PicoWriteRomHW_SSF2(u32 a,u32 d); -void PicoWriteRomHW_in1 (u32 a,u32 d); #endif -#if defined(EMU_C68K) && defined(EMU_M68K) -// cyclone debug mode +#ifdef EMU_CORE_DEBUG u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,}; int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0; extern unsigned int ppop; @@ -40,11 +37,13 @@ extern unsigned int ppop; #ifdef IO_STATS void log_io(unsigned int addr, int bits, int rw); +#elif defined(_MSC_VER) +#define log_io #else #define log_io(...) #endif -#if defined(EMU_C68K) || defined(EMU_A68K) +#if defined(EMU_C68K) static __inline int PicoMemBase(u32 pc) { int membase=0; @@ -68,29 +67,23 @@ static __inline int PicoMemBase(u32 pc) #endif -#ifdef EMU_A68K -extern u8 *OP_ROM=NULL,*OP_RAM=NULL; -#endif - -static u32 CPU_CALL PicoCheckPc(u32 pc) +PICO_INTERNAL u32 PicoCheckPc(u32 pc) { u32 ret=0; #if defined(EMU_C68K) - pc-=PicoCpu.membase; // Get real pc + pc-=PicoCpuCM68k.membase; // Get real pc // pc&=0xfffffe; pc&=~1; if ((pc<<8) == 0) + { + printf("%i:%03i: game crash detected @ %06x\n", Pico.m.frame_count, Pico.m.scanline, SekPc); return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off + } - PicoCpu.membase=PicoMemBase(pc&0x00ffffff); - PicoCpu.membase-=pc&0xff000000; - - ret = PicoCpu.membase+pc; -#elif defined(EMU_A68K) - OP_ROM=(u8 *)PicoMemBase(pc); + PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff); + PicoCpuCM68k.membase-=pc&0xff000000; - // don't bother calling us back unless it's outside the 64k segment - M68000_regs.AsmBank=(pc>>16); + ret = PicoCpuCM68k.membase+pc; #endif return ret; } @@ -110,25 +103,120 @@ PICO_INTERNAL_ASM void PicoMemReset(void) // ----------------------------------------------------------------- -#ifndef _ASM_MEMORY_C -// address must already be checked -static int SRAMRead(u32 a) +int PadRead(int i) { - u8 *d = SRam.data-SRam.start+a; - return (d[0]<<8)|d[1]; + int pad,value,data_reg; + pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU + data_reg=Pico.ioports[i+1]; + + // orr the bits, which are set as output + value = data_reg&(Pico.ioports[i+4]|0x80); + + if (PicoOpt & POPT_6BTN_PAD) + { + int phase = Pico.m.padTHPhase[i]; + + if(phase == 2 && !(data_reg&0x40)) { // TH + value|=(pad&0xc0)>>2; // ?0SA 0000 + return value; + } else if(phase == 3) { + if(data_reg&0x40) + value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ + else + value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111 + return value; + } + } + + if(data_reg&0x40) // TH + value|=(pad&0x3f); // ?1CB RLDU + else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU + + return value; // will mirror later } -#endif -// for nonstandard reads #ifndef _ASM_MEMORY_C static #endif -u32 OtherRead16End(u32 a, int realsize) +u32 SRAMRead(u32 a) +{ + unsigned int sreg = Pico.m.sram_reg; + if (!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM + elprintf(EL_SRAMIO, "normal sram detected."); + Pico.m.sram_reg|=0x10; // should be normal SRAM + } + if (sreg & 4) // EEPROM read + return SRAMReadEEPROM(); + else // if(sreg & 1) // (sreg&5) is one of prerequisites + return *(u8 *)(SRam.data-SRam.start+a); +} + +#ifndef _ASM_MEMORY_C +static +#endif +u32 SRAMRead16(u32 a) +{ + u32 d; + if (Pico.m.sram_reg & 4) { + d = SRAMReadEEPROM(); + d |= d << 8; + } else { + u8 *pm=(u8 *)(SRam.data-SRam.start+a); + d =*pm++ << 8; + d|=*pm++; + } + return d; +} + +static void SRAMWrite(u32 a, u32 d) +{ + unsigned int sreg = Pico.m.sram_reg; + if(!(sreg & 0x10)) { + // not detected SRAM + if((a&~1)==0x200000) { + elprintf(EL_SRAMIO, "eeprom detected."); + sreg|=4; // this should be a game with EEPROM (like NBA Jam) + SRam.start=0x200000; SRam.end=SRam.start+1; + } else + elprintf(EL_SRAMIO, "normal sram detected."); + sreg|=0x10; + Pico.m.sram_reg=sreg; + } + if(sreg & 4) { // EEPROM write + // this diff must be at most 16 for NBA Jam to work + if(SekCyclesDoneT()-lastSSRamWrite < 16) { + // just update pending state + elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite); + SRAMUpdPending(a, d); + } else { + int old=sreg; + SRAMWriteEEPROM(sreg>>6); // execute pending + SRAMUpdPending(a, d); + if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed + lastSSRamWrite = SekCyclesDoneT(); + } + } else if(!(sreg & 2)) { + u8 *pm=(u8 *)(SRam.data-SRam.start+a); + if(*pm != (u8)d) { + SRam.changed = 1; + *pm=(u8)d; + } + } +} + +// for nonstandard reads +static u32 OtherRead16End(u32 a, int realsize) { u32 d=0; - dprintf("strange r%i: %06x @%06x", realsize, a&0xffffff, SekPc); + // 32x test +/* + if (a == 0xa130ec) { d = 0x4d41; goto end; } // MA + else if (a == 0xa130ee) { d = 0x5253; goto end; } // RS + else if (a == 0xa15100) { d = 0x0080; goto end; } + else +*/ // for games with simple protection devices, discovered by Haze // some dumb detection is used, but that should be enough to make things work @@ -191,7 +279,7 @@ u32 OtherRead16End(u32 a, int realsize) } end: - dprintf("ret = %04x", d); + elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc); return d; } @@ -201,35 +289,9 @@ end: static void OtherWrite8End(u32 a,u32 d,int realsize) { // sram - //if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone()); - //if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT()); if(a >= SRam.start && a <= SRam.end) { - dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc); - unsigned int sreg = Pico.m.sram_reg; - if(!(sreg & 0x10)) { - // not detected SRAM - if((a&~1)==0x200000) { - Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam) - SRam.start=0x200000; SRam.end=SRam.start+1; - } - Pico.m.sram_reg|=0x10; - } - if(sreg & 4) { // EEPROM write - if(SekCyclesDoneT()-lastSSRamWrite < 46) { - // just update pending state - SRAMUpdPending(a, d); - } else { - SRAMWriteEEPROM(sreg>>6); // execute pending - SRAMUpdPending(a, d); - lastSSRamWrite = SekCyclesDoneT(); - } - } else if(!(sreg & 2)) { - u8 *pm=(u8 *)(SRam.data-SRam.start+a); - if(*pm != (u8)d) { - SRam.changed = 1; - *pm=(u8)d; - } - } + elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d, SekPc); + SRAMWrite(a, d); return; } @@ -242,31 +304,19 @@ static void OtherWrite8End(u32 a,u32 d,int realsize) #else // sram access register if(a == 0xA130F1) { - dprintf("sram reg=%02x", d); + elprintf(EL_SRAMIO, "sram reg=%02x", d); Pico.m.sram_reg &= ~3; Pico.m.sram_reg |= (u8)(d&3); return; } #endif - dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc); - - if(a >= 0xA13004 && a < 0xA13040) { - // dumb 12-in-1 or 4-in-1 banking support - int len; - a &= 0x3f; a <<= 16; - len = Pico.romsize - a; - if (len <= 0) return; // invalid/missing bank - if (len > 0x200000) len = 0x200000; // 2 megs - memcpy(Pico.rom, Pico.rom+a, len); // code which does this is in RAM so this is safe. - return; - } + elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc); // for games with simple protection devices, discovered by Haze - else if ((a>>22) == 1) + if ((a>>22) == 1) Pico.m.prot_bytes[(a>>2)&1] = (u8)d; } - #include "MemoryCmn.c" @@ -274,7 +324,7 @@ static void OtherWrite8End(u32 a,u32 d,int realsize) // Read Rom and read Ram #ifndef _ASM_MEMORY_C -PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a) +PICO_INTERNAL_ASM u32 PicoRead8(u32 a) { u32 d=0; @@ -282,20 +332,12 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a) a&=0xffffff; -#if !(defined(EMU_C68K) && defined(EMU_M68K)) +#ifndef EMU_CORE_DEBUG // sram - if(a >= SRam.start && a <= SRam.end) { - unsigned int sreg = Pico.m.sram_reg; - if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM - Pico.m.sram_reg|=0x10; // should be normal SRAM - } - if(sreg & 4) { // EEPROM read - d = SRAMReadEEPROM(); - goto end; - } else if(sreg & 1) { - d = *(u8 *)(SRam.data-SRam.start+a); - goto end; - } + if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) { + d = SRAMRead(a); + elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc); + goto end; } #endif @@ -303,22 +345,15 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a) log_io(a, 8, 0); if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram - d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8; - - end: + if ((a&0xe700e0)==0xc00000) // VDP + d=PicoVideoRead(a); + else d=OtherRead16(a&~1, 8); + if ((a&1)==0) d>>=8; - //if ((a&0xe0ffff)==0xe0AE57+0x69c) - // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc); - //if ((a&0xe0ffff)==0xe0a9ba+0x69c) - // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc); - - //if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT()); - //dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline); -#ifdef __debug_io - dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc); -#endif -#if defined(EMU_C68K) && defined(EMU_M68K) - if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) { +end: + elprintf(EL_IO, "r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc); +#ifdef EMU_CORE_DEBUG + if (a>=Pico.romsize) { lastread_a = a; lastread_d[lrp_cyc++&15] = (u8)d; } @@ -326,7 +361,7 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a) return d; } -PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a) +PICO_INTERNAL_ASM u32 PicoRead16(u32 a) { u32 d=0; @@ -334,10 +369,11 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a) a&=0xfffffe; -#if !(defined(EMU_C68K) && defined(EMU_M68K)) +#ifndef EMU_CORE_DEBUG // sram - if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) { - d = SRAMRead(a); + if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) { + d = SRAMRead16(a); + elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc); goto end; } #endif @@ -345,17 +381,14 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a) if (a=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) { +end: + elprintf(EL_IO, "r16: %06x, %04x @%06x", a&0xffffff, d, SekPc); +#ifdef EMU_CORE_DEBUG + if (a>=Pico.romsize) { lastread_a = a; lastread_d[lrp_cyc++&15] = d; } @@ -363,7 +396,7 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a) return d; } -PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a) +PICO_INTERNAL_ASM u32 PicoRead32(u32 a) { u32 d=0; @@ -372,22 +405,23 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a) a&=0xfffffe; // sram - if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) { - d = (SRAMRead(a)<<16)|SRAMRead(a+2); + if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) { + d = (SRAMRead16(a)<<16)|SRAMRead16(a+2); + elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc); goto end; } if (a=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) { +end: + elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc); +#ifdef EMU_CORE_DEBUG + if (a>=Pico.romsize) { lastread_a = a; lastread_d[lrp_cyc++&15] = d; } @@ -399,48 +433,41 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a) // ----------------------------------------------------------------- // Write Ram -static void CPU_CALL PicoWrite8(u32 a,u8 d) +#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS) +PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d) { -#ifdef __debug_io - dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc); -#endif -#if defined(EMU_C68K) && defined(EMU_M68K) + elprintf(EL_IO, "w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc); +#ifdef EMU_CORE_DEBUG lastwrite_cyc_d[lwp_cyc++&15] = d; #endif - //if ((a&0xe0ffff)==0xe0a9ba+0x69c) - // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc); if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram log_io(a, 8, 1); a&=0xffffff; - OtherWrite8(a,d,8); + OtherWrite8(a,d); } +#endif -void CPU_CALL PicoWrite16(u32 a,u16 d) +void PicoWrite16(u32 a,u16 d) { -#ifdef __debug_io - dprintf("w16: %06x, %04x", a&0xffffff, d); -#endif -#if defined(EMU_C68K) && defined(EMU_M68K) + elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d); +#ifdef EMU_CORE_DEBUG lastwrite_cyc_d[lwp_cyc++&15] = d; #endif - //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c) - // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc); if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram log_io(a, 16, 1); a&=0xfffffe; + if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; } // VDP OtherWrite16(a,d); } -static void CPU_CALL PicoWrite32(u32 a,u32 d) +static void PicoWrite32(u32 a,u32 d) { -#ifdef __debug_io - dprintf("w32: %06x, %08x", a&0xffffff, d); -#endif -#if defined(EMU_C68K) && defined(EMU_M68K) + elprintf(EL_IO, "w32: %06x, %08x", a&0xffffff, d); +#ifdef EMU_CORE_DEBUG lastwrite_cyc_d[lwp_cyc++&15] = d; #endif @@ -454,97 +481,121 @@ static void CPU_CALL PicoWrite32(u32 a,u32 d) log_io(a, 32, 1); a&=0xfffffe; + if ((a&0xe700e0)==0xc00000) + { + // VDP: + PicoVideoWrite(a, (u16)(d>>16)); + PicoVideoWrite(a+2,(u16)d); + return; + } + OtherWrite16(a, (u16)(d>>16)); OtherWrite16(a+2,(u16)d); } // ----------------------------------------------------------------- + +static void OtherWrite16End(u32 a,u32 d,int realsize) +{ + PicoWrite8Hook(a, d>>8, realsize); + PicoWrite8Hook(a+1,d&0xff, realsize); +} + +u32 (*PicoRead16Hook) (u32 a, int realsize) = OtherRead16End; +void (*PicoWrite8Hook) (u32 a, u32 d, int realsize) = OtherWrite8End; +void (*PicoWrite16Hook)(u32 a, u32 d, int realsize) = OtherWrite16End; + +PICO_INTERNAL void PicoMemResetHooks(void) +{ + // default unmapped/cart specific handlers + PicoRead16Hook = OtherRead16End; + PicoWrite8Hook = OtherWrite8End; + PicoWrite16Hook = OtherWrite16End; +} + +#ifdef EMU_M68K +static void m68k_mem_setup(void); +#endif + PICO_INTERNAL void PicoMemSetup(void) { -#ifdef EMU_C68K // Setup memory callbacks: - PicoCpu.checkpc=PicoCheckPc; - PicoCpu.fetch8 =PicoCpu.read8 =PicoRead8; - PicoCpu.fetch16=PicoCpu.read16=PicoRead16; - PicoCpu.fetch32=PicoCpu.read32=PicoRead32; - PicoCpu.write8 =PicoWrite8; - PicoCpu.write16=PicoWrite16; - PicoCpu.write32=PicoWrite32; -#endif -} - -#ifdef EMU_A68K -struct A68KInter -{ - u32 unknown; - u8 (__fastcall *Read8) (u32 a); - u16 (__fastcall *Read16)(u32 a); - u32 (__fastcall *Read32)(u32 a); - void (__fastcall *Write8) (u32 a,u8 d); - void (__fastcall *Write16) (u32 a,u16 d); - void (__fastcall *Write32) (u32 a,u32 d); - void (__fastcall *ChangePc)(u32 a); - u8 (__fastcall *PcRel8) (u32 a); - u16 (__fastcall *PcRel16)(u32 a); - u32 (__fastcall *PcRel32)(u32 a); - u16 (__fastcall *Dir16)(u32 a); - u32 (__fastcall *Dir32)(u32 a); -}; - -struct A68KInter a68k_memory_intf= -{ - 0, - PicoRead8, - PicoRead16, - PicoRead32, - PicoWrite8, - PicoWrite16, - PicoWrite32, - PicoCheckPc, - PicoRead8, - PicoRead16, - PicoRead32, - PicoRead16, // unused - PicoRead32, // unused -}; +#ifdef EMU_C68K + PicoCpuCM68k.checkpc=PicoCheckPc; + PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8; + PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16; + PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32; + PicoCpuCM68k.write8 =PicoWrite8; + PicoCpuCM68k.write16=PicoWrite16; + PicoCpuCM68k.write32=PicoWrite32; +#endif +#ifdef EMU_F68K + PicoCpuFM68k.read_byte =PicoRead8; + PicoCpuFM68k.read_word =PicoRead16; + PicoCpuFM68k.read_long =PicoRead32; + PicoCpuFM68k.write_byte=PicoWrite8; + PicoCpuFM68k.write_word=PicoWrite16; + PicoCpuFM68k.write_long=PicoWrite32; + + // setup FAME fetchmap + { + int i; + // by default, point everything to first 64k of ROM + for (i = 0; i < M68K_FETCHBANK1; i++) + PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS)); + // now real ROM + for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++) + PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom; + // .. and RAM + for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++) + PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS)); + } #endif - #ifdef EMU_M68K -unsigned int m68k_read_pcrelative_CD8 (unsigned int a); -unsigned int m68k_read_pcrelative_CD16(unsigned int a); -unsigned int m68k_read_pcrelative_CD32(unsigned int a); + m68k_mem_setup(); +#endif +} -// these are allowed to access RAM -static unsigned int m68k_read_8 (unsigned int a, int do_fake) { +/* some nasty things below :( */ +#ifdef EMU_M68K +unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL; +unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL; +unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL; +void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL; +void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL; +void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL; +unsigned int (*pm68k_read_memory_pcr_8) (unsigned int address) = NULL; +unsigned int (*pm68k_read_memory_pcr_16)(unsigned int address) = NULL; +unsigned int (*pm68k_read_memory_pcr_32)(unsigned int address) = NULL; + +// these are here for core debugging mode +static unsigned int m68k_read_8 (unsigned int a, int do_fake) +{ a&=0xffffff; - if(PicoMCD&1) return m68k_read_pcrelative_CD8(a); - if(a= 228) + z80_scanline++, z80_scanline_cycles += 228; + return z80_scanline; + } + + if (Pico.m.scanline != -1) + return Pico.m.scanline; + + return vcounts[SekCyclesDone()>>8]; } -unsigned int m68k_read_memory_32(unsigned int address) +/* probably not should be in this file, but it's near related code here */ +void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new) { - return (PicoMCD&1) ? PicoReadCD32w(address) : PicoRead32(address); + int xcycles = z80_cycles << 8; + + /* check for overflows */ + if ((mode_old & 4) && xcycles > timer_a_next_oflow) + ym2612.OPN.ST.status |= 1; + + if ((mode_old & 8) && xcycles > timer_b_next_oflow) + ym2612.OPN.ST.status |= 2; + + /* update timer a */ + if (mode_old & 1) + while (xcycles >= timer_a_next_oflow) + timer_a_next_oflow += timer_a_step; + + if ((mode_old ^ mode_new) & 1) // turning on/off + { + if (mode_old & 1) { + timer_a_offset = timer_a_next_oflow - xcycles; + timer_a_next_oflow = 0x70000000; + } + else + timer_a_next_oflow = xcycles + timer_a_offset; + } + if (mode_new & 1) + elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles); + + /* update timer b */ + if (mode_old & 2) + while (xcycles >= timer_b_next_oflow) + timer_b_next_oflow += timer_b_step; + + if ((mode_old ^ mode_new) & 2) + { + if (mode_old & 2) { + timer_b_offset = timer_b_next_oflow - xcycles; + timer_b_next_oflow = 0x70000000; + } + else + timer_b_next_oflow = xcycles + timer_b_offset; + } + if (mode_new & 2) + elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles); } -void m68k_write_memory_8(unsigned int address, unsigned int value) +// ym2612 DAC and timer I/O handlers for z80 +int ym2612_write_local(u32 a, u32 d, int is_from_z80) { - if (PicoMCD&1) PicoWriteCD8w(address, (u8)value); else PicoWrite8(address, (u8)value); + int addr; + + a &= 3; + if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */ + { + int scanline = get_scanline(is_from_z80); + //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80); + ym2612.dacout = ((int)d - 0x80) << 6; + if (PsndOut && ym2612.dacen && scanline >= PsndDacLine) + PsndDoDAC(scanline); + return 0; + } + + switch (a) + { + case 0: /* address port 0 */ + ym2612.OPN.ST.address = d; + ym2612.addr_A1 = 0; +#ifdef __GP2X__ + if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1); +#endif + return 0; + + case 1: /* data port 0 */ + if (ym2612.addr_A1 != 0) + return 0; + + addr = ym2612.OPN.ST.address; + ym2612.REGS[addr] = d; + + switch (addr) + { + case 0x24: // timer A High 8 + case 0x25: { // timer A Low 2 + int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2)) + : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3)); + if (ym2612.OPN.ST.TA != TAnew) + { + //elprintf(EL_STATUS, "timer a set %i", TAnew); + ym2612.OPN.ST.TA = TAnew; + //ym2612.OPN.ST.TAC = (1024-TAnew)*18; + //ym2612.OPN.ST.TAT = 0; + // + timer_a_step = timer_a_offset = 16466 * (1024 - TAnew); + if (ym2612.OPN.ST.mode & 1) { + int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone()); + timer_a_next_oflow = (cycles << 8) + timer_a_step; + } + elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8); + } + return 0; + } + case 0x26: // timer B + if (ym2612.OPN.ST.TB != d) { + //elprintf(EL_STATUS, "timer b set %i", d); + ym2612.OPN.ST.TB = d; + //ym2612.OPN.ST.TBC = (256-d)<<4; + //ym2612.OPN.ST.TBC *= 18; + //ym2612.OPN.ST.TBT = 0; + timer_b_step = timer_b_offset = 262800 * (256 - d); // 262881 + if (ym2612.OPN.ST.mode & 2) { + int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone()); + timer_b_next_oflow = (cycles << 8) + timer_b_step; + } + elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8); + } + return 0; + case 0x27: { /* mode, timer control */ + int old_mode = ym2612.OPN.ST.mode; + int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone()); + ym2612.OPN.ST.mode = d; + + elprintf(EL_YMTIMER, "st mode %02x", d); + ym2612_sync_timers(cycles, old_mode, d); + + /* reset Timer a flag */ + if (d & 0x10) + ym2612.OPN.ST.status &= ~1; + + /* reset Timer b flag */ + if (d & 0x20) + ym2612.OPN.ST.status &= ~2; + + if ((d ^ old_mode) & 0xc0) { +#ifdef __GP2X__ + if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, get_scanline(is_from_z80)); +#endif + return 1; + } + return 0; + } + case 0x2b: { /* DAC Sel (YM2612) */ + int scanline = get_scanline(is_from_z80); + ym2612.dacen = d & 0x80; + if (d & 0x80) PsndDacLine = scanline; +#ifdef __GP2X__ + if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline); +#endif + return 0; + } + } + break; + + case 2: /* address port 1 */ + ym2612.OPN.ST.address = d; + ym2612.addr_A1 = 1; +#ifdef __GP2X__ + if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1); +#endif + return 0; + + case 3: /* data port 1 */ + if (ym2612.addr_A1 != 1) + return 0; + + addr = ym2612.OPN.ST.address | 0x100; + ym2612.REGS[addr] = d; + break; + } + +#ifdef __GP2X__ + if (PicoOpt & POPT_EXT_FM) + return YM2612Write_940(a, d, get_scanline(is_from_z80)); +#endif + return YM2612Write_(a, d); } -void m68k_write_memory_16(unsigned int address, unsigned int value) + +#define ym2612_read_local() \ + if (xcycles >= timer_a_next_oflow) \ + ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \ + if (xcycles >= timer_b_next_oflow) \ + ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2 + +u32 ym2612_read_local_z80(void) { - if (PicoMCD&1) PicoWriteCD16w(address,(u16)value); else PicoWrite16(address,(u16)value); + int xcycles = z80_cyclesDone() << 8; + + ym2612_read_local(); + + elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status, + timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228); + return ym2612.OPN.ST.status; } -void m68k_write_memory_32(unsigned int address, unsigned int value) +u32 ym2612_read_local_68k(void) { - if (PicoMCD&1) PicoWriteCD32w(address, value); else PicoWrite32(address, value); + int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8; + + ym2612_read_local(); + + elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status, + timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228); + return ym2612.OPN.ST.status; } -#endif -#endif // EMU_M68K +// TODO: new ym2612 savestates, also save timers +void ym2612_unpack_state(void) +{ + int i; + YM2612PicoStateLoad(); + + // feed all the registers and update internal state + for (i = 0x20; i < 0xC0; i++) { + ym2612_write_local(0, i, 0); + ym2612_write_local(1, ym2612.REGS[i], 0); + } + for (i = 0x30; i < 0xC0; i++) { + ym2612_write_local(2, i, 0); + ym2612_write_local(3, ym2612.REGS[i|0x100], 0); + } +} // ----------------------------------------------------------------- // z80 memhandlers @@ -643,49 +938,49 @@ PICO_INTERNAL unsigned char z80_read(unsigned short a) if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald) { - if(PicoOpt&1) ret = (u8) YM2612Read(); - goto end; + if (PicoOpt&POPT_EN_FM) ret = ym2612_read_local_z80(); + return ret; } if (a>=0x8000) { + extern u32 PicoReadM68k8(u32 a); u32 addr68k; addr68k=Pico.m.z80_bank68k<<15; addr68k+=a&0x7fff; - ret = (u8) PicoRead8(addr68k); - //dprintf("z80->68k w8 : %06x, %02x", addr68k, ret); - goto end; + if (addr68k < Pico.romsize) { ret = Pico.rom[addr68k^1]; goto bnkend; } + elprintf(EL_ANOMALY, "z80->68k upper read [%06x] %02x", addr68k, ret); + if (PicoAHW & PAHW_MCD) + ret = PicoReadM68k8(addr68k); + else ret = PicoRead8(addr68k); +bnkend: + elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret); + return ret; } - // should not be needed || dprintf("z80_read RAM"); - if (a<0x4000) { ret = (u8) Pico.zram[a&0x1fff]; goto end; } + // should not be needed, cores should be able to access RAM themselves + if (a<0x4000) return Pico.zram[a&0x1fff]; -end: + elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret); return ret; } -PICO_INTERNAL unsigned short z80_read16(unsigned short a) -{ - //dprintf("z80_read16"); - - return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) ); -} - +#ifndef _USE_CZ80 PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a) +#else +PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data) +#endif { - //if (a<0x4000) - // dprintf("z80 w8 : %06x, %02x @%04x", a, data, mz80GetRegisterValue(NULL, 0)); - if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald) { - if(PicoOpt&1) emustatus|=YM2612Write(a, data); + if(PicoOpt&POPT_EN_FM) emustatus|=ym2612_write_local(a, data, 1) & 1; return; } if ((a&0xfff9)==0x7f11) // 7f11 7f13 7f15 7f17 { - if(PicoOpt&2) SN76496Write(data); + if(PicoOpt&POPT_EN_PSG) SN76496Write(data); return; } @@ -699,23 +994,33 @@ PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a) if (a>=0x8000) { + extern void PicoWriteM68k8(u32 a,u8 d); u32 addr68k; addr68k=Pico.m.z80_bank68k<<15; addr68k+=a&0x7fff; - PicoWrite8(addr68k, data); - //dprintf("z80->68k w8 : %06x, %02x", addr68k, data); + elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data); + if (PicoAHW & PAHW_MCD) + PicoWriteM68k8(addr68k, data); + else PicoWrite8(addr68k, data); return; } - // should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr); + // should not be needed if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; } + + elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data); } -PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a) +#ifndef _USE_CZ80 +PICO_INTERNAL unsigned short z80_read16(unsigned short a) { - //dprintf("z80_write16"); + return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) ); +} +PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a) +{ z80_write((unsigned char) data,a); z80_write((unsigned char)(data>>8),(u16)(a+1)); } +#endif