X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2Fcarthw%2Fsvp%2Fcompiler.c;h=0cdd6ad44739d72fdc641b4d9aa83880f3c2dca4;hb=e122fae6f47c4ca4fce5a178d6d2055b3cef6423;hp=527647e5b249eb7571fc44b256f03a3a40f012a8;hpb=6e39239fb9c95c8e556bdc3ab26307679c246436;p=picodrive.git diff --git a/Pico/carthw/svp/compiler.c b/Pico/carthw/svp/compiler.c index 527647e..0cdd6ad 100644 --- a/Pico/carthw/svp/compiler.c +++ b/Pico/carthw/svp/compiler.c @@ -12,7 +12,7 @@ static int nblocks = 0; static int iram_context = 0; #ifndef ARM -#define DUMP_BLOCK 0x341e +#define DUMP_BLOCK 0x2018 unsigned int tcache[512*1024]; void regfile_load(void){} void regfile_store(void){} @@ -490,6 +490,88 @@ static in_func *in_funcs[0x80] = NULL, op79, NULL, NULL, op7c, NULL, NULL, NULL, }; + +static u32 ssp_pm_read(int reg) +{ + u32 d = 0, mode; + + if (ssp->emu_status & SSP_PMC_SET) + { + ssp->pmac_read[reg] = rPMC.v; + ssp->emu_status &= ~SSP_PMC_SET; + //elprintf("set PM%i %08x", ssp->pmac_read[reg]); + return 0; + } + + //elprintf("rd PM%i %08x", ssp->pmac_read[reg]); + // just in case + ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; + + mode = ssp->pmac_read[reg]>>16; + if ((mode & 0xfff0) == 0x0800) // ROM + { + d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff]; + ssp->pmac_read[reg] += 1; + } + else if ((mode & 0x47ff) == 0x0018) // DRAM + { + unsigned short *dram = (unsigned short *)svp->dram; + int inc = get_inc(mode); + d = dram[ssp->pmac_read[reg]&0xffff]; + ssp->pmac_read[reg] += inc; + } + + // PMC value corresponds to last PMR accessed + rPMC.v = ssp->pmac_read[reg]; + + return d; +} + +static void ssp_pm_write(u32 d, int reg) +{ + unsigned short *dram; + int mode, addr; + + if (ssp->emu_status & SSP_PMC_SET) + { + ssp->pmac_write[reg] = rPMC.v; + ssp->emu_status &= ~SSP_PMC_SET; + return; + } + + // just in case + ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; + + dram = (unsigned short *)svp->dram; + mode = ssp->pmac_write[reg]>>16; + addr = ssp->pmac_write[reg]&0xffff; + if ((mode & 0x43ff) == 0x0018) // DRAM + { + int inc = get_inc(mode); + if (mode & 0x0400) { + overwrite_write(dram[addr], d); + } else dram[addr] = d; + ssp->pmac_write[reg] += inc; + } + else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc + { + if (mode & 0x0400) { + overwrite_write(dram[addr], d); + } else dram[addr] = d; + ssp->pmac_write[reg] += (addr&1) ? 31 : 1; + } + else if ((mode & 0x47ff) == 0x001c) // IRAM + { + int inc = get_inc(mode); + ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d; + ssp->pmac_write[reg] += inc; + ssp->drc.iram_dirty = 1; + } + + rPMC.v = ssp->pmac_write[reg]; +} + + // ----------------------------------------------------- static unsigned char iram_context_map[] = @@ -533,6 +615,10 @@ static struct { ssp_reg_t gr[8]; unsigned char r[8]; + unsigned int pmac_read[5]; + unsigned int pmac_write[5]; + ssp_reg_t pmc; + unsigned int emu_status; } known_regs; #define KRREG_X (1 << SSP_X) @@ -545,12 +631,24 @@ static struct #define KRREG_PR0 (1 << 8) #define KRREG_PR4 (1 << 12) #define KRREG_AL (1 << 16) +#define KRREG_PMCM (1 << 18) /* only mode word of PMC */ +#define KRREG_PMC (1 << 19) +#define KRREG_PM0R (1 << 20) +#define KRREG_PM1R (1 << 21) +#define KRREG_PM2R (1 << 22) +#define KRREG_PM3R (1 << 23) +#define KRREG_PM4R (1 << 24) +#define KRREG_PM0W (1 << 25) +#define KRREG_PM1W (1 << 26) +#define KRREG_PM2W (1 << 27) +#define KRREG_PM3W (1 << 28) +#define KRREG_PM4W (1 << 29) /* bitfield of known register values */ static u32 known_regb = 0; /* known vals, which need to be flushed - * (only ST, P, r0-r7) + * (only ST, P, r0-r7, PMCx, PMxR, PMxW) * ST means flags are being held in ARM PSR * P means that it needs to be recalculated */ @@ -579,7 +677,8 @@ static void hostreg_sspreg_changed(int sspreg) } -#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x] +#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x] +#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x)) static void tr_unhandled(void) { @@ -590,16 +689,17 @@ static void tr_unhandled(void) exit(1); } -/* update P, if needed. Trashes r1 */ +/* update P, if needed. Trashes r0 */ static void tr_flush_dirty_P(void) { // TODO: const regs if (!(dirty_regb & KRREG_P)) return; EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16 - EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16 - EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15 - EOP_MUL(10, 1, 10); // mul r10, r1, r10 + EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16 + EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15 + EOP_MUL(10, 0, 10); // mul r10, r0, r10 dirty_regb &= ~KRREG_P; + hostreg_r[0] = -1; } /* write dirty pr to host reg. Nothing is trashed */ @@ -693,7 +793,44 @@ static void tr_mov16_cond(int cond, int r, int val) hostreg_r[r] = -1; } -/* read bank word to r0. Thrashes r1. */ +/* trashes r0 */ +static void tr_flush_dirty_pmcrs(void) +{ + u32 i, val = (u32)-1; + if (!(dirty_regb & 0x3ff80000)) return; + + if (dirty_regb & KRREG_PMC) { + val = known_regs.pmc.v; + emit_mov_const(A_COND_AL, 1, val); + EOP_STR_IMM(1,7,0x400+SSP_PMC*4); + + if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) { + printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n"); + tr_unhandled(); + } + } + for (i = 0; i < 5; i++) + { + if (dirty_regb & (1 << (20+i))) { + if (val != known_regs.pmac_read[i]) { + val = known_regs.pmac_read[i]; + emit_mov_const(A_COND_AL, 1, val); + } + EOP_STR_IMM(1,7,0x454+i*4); // pmac_read + } + if (dirty_regb & (1 << (25+i))) { + if (val != known_regs.pmac_write[i]) { + val = known_regs.pmac_write[i]; + emit_mov_const(A_COND_AL, 1, val); + } + EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write + } + } + dirty_regb &= ~0x3ff80000; + hostreg_r[1] = -1; +} + +/* read bank word to r0 (upper bits zero). Thrashes r1. */ static void tr_bank_read(int addr) /* word addr 0-0x1ff */ { int breg = 7; @@ -740,9 +877,16 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo, int count) { int reg = (r < 4) ? 8 : 9; tr_release_pr(r); - tr_flush_dirty_ST(); - EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70 - EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80 + if (dirty_regb & KRREG_ST) { + // avoid flushing ARM flags + EOP_AND_IMM(1, 6, 0, 0x70); + EOP_SUB_IMM(1, 1, 0, 0x10); + EOP_AND_IMM(1, 1, 0, 0x70); + EOP_ADD_IMM(1, 1, 0, 0x10); + } else { + EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70 + EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80 + } EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000 @@ -776,7 +920,7 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo, int count) /* handle writes r0 to (rX). Trashes r1. * fortunately we can ignore modulo increment modes for writes. */ -static void tr_rX_write1(int op) +static void tr_rX_write(int op) { if ((op&3) == 3) { @@ -823,12 +967,45 @@ static void tr_rX_read(int r, int mod) if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr else EOP_ADD_REG_LSL(1,7,1,1); EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1] - hostreg_r[1] = -1; + hostreg_r[0] = hostreg_r[1] = -1; } tr_ptrr_mod(r, mod, 1, 1); } } +/* read ((rX)) to r0. Trashes r1,r2. */ +static void tr_rX_read2(int op) +{ + int r = (op&3) | ((op>>6)&4); // src + + if ((r&3) == 3) { + tr_bank_read((op&0x100) | ((op>>2)&3)); + } else if (known_regb & (1 << (r+8))) { + tr_bank_read((op&0x100) | known_regs.r[r]); + } else { + int reg = (r < 4) ? 8 : 9; + int ror = ((4 - (r&3))*8) & 0x1f; + EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, + if (r >= 4) + EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<>2)&3)); + } else if (known_regb & (1 << (r+8))) { + tr_bank_write((op&0x100) | known_regs.r[r]); + } else { + EOP_STRH_SIMPLE(0,1); // strh r0, [r1] + hostreg_r[1] = -1; + } + EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2] + hostreg_r[0] = hostreg_r[2] = -1; +} /* get ARM cond which would mean that SSP cond is satisfied. No trash. */ static int tr_cond_check(int op) @@ -864,6 +1041,23 @@ static int tr_neg_cond(int cond) return 0; } +static int tr_aop_ssp2arm(int op) +{ + switch (op) { + case 1: return A_OP_SUB; + case 3: return A_OP_CMP; + case 4: return A_OP_ADD; + case 5: return A_OP_AND; + case 6: return A_OP_ORR; + case 7: return A_OP_EOR; + } + + tr_unhandled(); + return 0; +} + +// ----------------------------------------------------- + // SSP_GR0, SSP_X, SSP_Y, SSP_A, // SSP_ST, SSP_STACK, SSP_PC, SSP_P, //@ r4: XXYY @@ -873,12 +1067,12 @@ static int tr_neg_cond(int cond) //@ r10: P // read general reg to r0. Trashes r1 -static void tr_GR0_to_r0(void) +static void tr_GR0_to_r0(int op) { tr_mov16(0, 0xffff); } -static void tr_X_to_r0(void) +static void tr_X_to_r0(int op) { if (hostreg_r[0] != (SSP_X<<16)) { EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16 @@ -886,7 +1080,7 @@ static void tr_X_to_r0(void) } } -static void tr_Y_to_r0(void) +static void tr_Y_to_r0(int op) { // TODO.. if (hostreg_r[0] != (SSP_Y<<16)) { @@ -895,7 +1089,7 @@ static void tr_Y_to_r0(void) } } -static void tr_A_to_r0(void) +static void tr_A_to_r0(int op) { if (hostreg_r[0] != (SSP_A<<16)) { EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH @@ -903,7 +1097,7 @@ static void tr_A_to_r0(void) } } -static void tr_ST_to_r0(void) +static void tr_ST_to_r0(int op) { // VR doesn't need much accuracy here.. EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4 @@ -911,7 +1105,7 @@ static void tr_ST_to_r0(void) hostreg_r[0] = -1; } -static void tr_STACK_to_r0(void) +static void tr_STACK_to_r0(int op) { // 448 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29 @@ -922,21 +1116,161 @@ static void tr_STACK_to_r0(void) hostreg_r[0] = hostreg_r[1] = -1; } -static void tr_PC_to_r0(void) +static void tr_PC_to_r0(int op) { tr_mov16(0, known_regs.gr[SSP_PC].h); } -static void tr_P_to_r0(void) +static void tr_P_to_r0(int op) { tr_flush_dirty_P(); EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16 hostreg_r[0] = -1; } -typedef void (tr_read_func)(void); +static void tr_AL_to_r0(int op) +{ + if (op == 0x000f) { + if (known_regb & KRREG_PMC) { + known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); + } else { + EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status + EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR); + EOP_STR_IMM(0,7,0x484); + } + } + + if (hostreg_r[0] != (SSP_AL<<16)) { + EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5 + hostreg_r[0] = SSP_AL<<16; + } +} + +static void tr_PMX_to_r0(int reg) +{ + if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) + { + known_regs.pmac_read[reg] = known_regs.pmc.v; + known_regs.emu_status &= ~SSP_PMC_SET; + known_regb |= 1 << (20+reg); + dirty_regb |= 1 << (20+reg); + return; + } + + if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg)))) + { + u32 pmcv = known_regs.pmac_read[reg]; + int mode = pmcv>>16; + known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; + + if ((mode & 0xfff0) == 0x0800) + { + EOP_LDR_IMM(1,7,0x488); // rom_ptr + emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1); + EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] + known_regs.pmac_read[reg] += 1; + } + else if ((mode & 0x47ff) == 0x0018) // DRAM + { + int inc = get_inc(mode); + EOP_LDR_IMM(1,7,0x490); // dram_ptr + emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1); + EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] + if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection + { + int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08; + tr_flush_dirty_ST(); + EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status + EOP_TST_REG_SIMPLE(0,0); + EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // addeq r11, r11, #1024 + EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08 + EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status + } + known_regs.pmac_read[reg] += inc; + } + else + { + tr_unhandled(); + } + known_regs.pmc.v = known_regs.pmac_read[reg]; + //known_regb |= KRREG_PMC; + dirty_regb |= KRREG_PMC; + dirty_regb |= 1 << (20+reg); + hostreg_r[0] = hostreg_r[1] = -1; + return; + } + + known_regb &= ~KRREG_PMC; + dirty_regb &= ~KRREG_PMC; + known_regb &= ~(1 << (20+reg)); + dirty_regb &= ~(1 << (20+reg)); + + // call the C code to handle this + tr_flush_dirty_ST(); + //tr_flush_dirty_pmcrs(); + tr_mov16(0, reg); + emit_call(ssp_pm_read); + hostreg_clear(); +} + +static void tr_PM0_to_r0(int op) +{ + tr_PMX_to_r0(0); +} + +static void tr_PM1_to_r0(int op) +{ + tr_PMX_to_r0(1); +} + +static void tr_PM2_to_r0(int op) +{ + tr_PMX_to_r0(2); +} + +static void tr_XST_to_r0(int op) +{ + EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400 + EOP_LDRH_IMM(0, 0, SSP_XST*4+2); +} + +static void tr_PM4_to_r0(int op) +{ + tr_PMX_to_r0(4); +} -static tr_read_func *tr_read_funcs[8] = +static void tr_PMC_to_r0(int op) +{ + if (known_regb & KRREG_PMC) + { + if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { + known_regs.emu_status |= SSP_PMC_SET; + known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; + // do nothing - this is handled elsewhere + } else { + tr_mov16(0, known_regs.pmc.l); + known_regs.emu_status |= SSP_PMC_HAVE_ADDR; + } + } + else + { + EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status + tr_flush_dirty_ST(); + if (op != 0x000e) + EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4); + EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); + EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. + EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. + EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. + EOP_STR_IMM(1,7,0x484); + hostreg_r[0] = hostreg_r[1] = -1; + } +} + + +typedef void (tr_read_func)(int op); + +static tr_read_func *tr_read_funcs[16] = { tr_GR0_to_r0, tr_X_to_r0, @@ -945,7 +1279,15 @@ static tr_read_func *tr_read_funcs[8] = tr_ST_to_r0, tr_STACK_to_r0, tr_PC_to_r0, - tr_P_to_r0 + tr_P_to_r0, + tr_PM0_to_r0, + tr_PM1_to_r0, + tr_PM2_to_r0, + tr_XST_to_r0, + tr_PM4_to_r0, + (tr_read_func *)tr_unhandled, + tr_PMC_to_r0, + tr_AL_to_r0 }; @@ -1022,9 +1364,158 @@ static void tr_r0_to_PC(int const_val) hostreg_r[1] = -1; } +static void tr_r0_to_AL(int const_val) +{ + EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 + EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16 + EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16 + hostreg_sspreg_changed(SSP_AL); + if (const_val != -1) { + known_regs.gr[SSP_A].l = const_val; + known_regb |= 1 << SSP_AL; + } else + known_regb &= ~(1 << SSP_AL); +} + +static void tr_r0_to_PMX(int reg) +{ +#if 1 + if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) + { + known_regs.pmac_write[reg] = known_regs.pmc.v; + known_regs.emu_status &= ~SSP_PMC_SET; + known_regb |= 1 << (25+reg); + dirty_regb |= 1 << (25+reg); + return; + } +#endif +#if 1 + if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg)))) + { + int mode, addr; + + known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; + + mode = known_regs.pmac_write[reg]>>16; + addr = known_regs.pmac_write[reg]&0xffff; + if ((mode & 0x43ff) == 0x0018) // DRAM + { + int inc = get_inc(mode); + if (mode & 0x0400) tr_unhandled(); + EOP_LDR_IMM(1,7,0x490); // dram_ptr + emit_mov_const(A_COND_AL, 2, addr<<1); + EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] + known_regs.pmac_write[reg] += inc; + } + else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc + { + if (mode & 0x0400) tr_unhandled(); + EOP_LDR_IMM(1,7,0x490); // dram_ptr + emit_mov_const(A_COND_AL, 2, addr<<1); + EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] + known_regs.pmac_write[reg] += (addr&1) ? 31 : 1; + } + else if ((mode & 0x47ff) == 0x001c) // IRAM + { + int inc = get_inc(mode); + EOP_LDR_IMM(1,7,0x48c); // iram_ptr + emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1); + EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] + EOP_MOV_IMM(1,0,1); + EOP_STR_IMM(1,7,0x494); // iram_dirty + known_regs.pmac_write[reg] += inc; + } + else + tr_unhandled(); + + known_regs.pmc.v = known_regs.pmac_write[reg]; + //known_regb |= KRREG_PMC; + dirty_regb |= KRREG_PMC; + dirty_regb |= 1 << (25+reg); + hostreg_r[1] = hostreg_r[2] = -1; + return; + } + + known_regb &= ~KRREG_PMC; + dirty_regb &= ~KRREG_PMC; + known_regb &= ~(1 << (25+reg)); + dirty_regb &= ~(1 << (25+reg)); +#else +tr_flush_dirty_pmcrs(); +hostreg_clear(); +known_regb &= ~KRREG_PMC; +dirty_regb &= ~KRREG_PMC; +known_regb &= ~(1 << (25+reg)); +dirty_regb &= ~(1 << (25+reg)); +#endif + + + // call the C code to handle this + tr_flush_dirty_ST(); + //tr_flush_dirty_pmcrs(); + tr_mov16(1, reg); + emit_call(ssp_pm_write); + hostreg_clear(); +} + +static void tr_r0_to_PM0(int const_val) +{ + tr_r0_to_PMX(0); +} + +static void tr_r0_to_PM1(int const_val) +{ + tr_r0_to_PMX(1); +} + +static void tr_r0_to_PM2(int const_val) +{ + tr_r0_to_PMX(2); +} + +static void tr_r0_to_PM4(int const_val) +{ + tr_r0_to_PMX(4); +} + +static void tr_r0_to_PMC(int const_val) +{ + if ((known_regb & KRREG_PMC) && const_val != -1) + { + if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { + known_regs.emu_status |= SSP_PMC_SET; + known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; + known_regs.pmc.h = const_val; + } else { + known_regs.emu_status |= SSP_PMC_HAVE_ADDR; + known_regs.pmc.l = const_val; + } + } + else + { + tr_flush_dirty_ST(); + if (known_regb & KRREG_PMC) { + emit_mov_const(A_COND_AL, 1, known_regs.pmc.v); + EOP_STR_IMM(1,7,0x400+SSP_PMC*4); + known_regb &= ~KRREG_PMC; + dirty_regb &= ~KRREG_PMC; + } + EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status + EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400 + EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); + EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC] + EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2); + EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. + EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. + EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. + EOP_STR_IMM(1,7,0x484); + hostreg_r[1] = hostreg_r[2] = -1; + } +} + typedef void (tr_write_func)(int const_val); -static tr_write_func *tr_write_funcs[8] = +static tr_write_func *tr_write_funcs[16] = { tr_r0_to_GR0, tr_r0_to_X, @@ -1033,13 +1524,111 @@ static tr_write_func *tr_write_funcs[8] = tr_r0_to_ST, tr_r0_to_STACK, tr_r0_to_PC, - (tr_write_func *)tr_unhandled + (tr_write_func *)tr_unhandled, + tr_r0_to_PM0, + tr_r0_to_PM1, + tr_r0_to_PM2, + (tr_write_func *)tr_unhandled, + tr_r0_to_PM4, + (tr_write_func *)tr_unhandled, + tr_r0_to_PMC, + tr_r0_to_AL }; +static void tr_mac_load_XY(int op) +{ + tr_rX_read(op&3, (op>>2)&3); // X + EOP_MOV_REG_LSL(4, 0, 16); + tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y + EOP_ORR_REG_SIMPLE(4, 0); + dirty_regb |= KRREG_P; + hostreg_sspreg_changed(SSP_X); + hostreg_sspreg_changed(SSP_Y); + known_regb &= ~KRREG_X; + known_regb &= ~KRREG_Y; +} + +// ----------------------------------------------------- + +static int tr_detect_set_pm(unsigned int op, int *pc, int imm) +{ + u32 pmcv, tmpv; + if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0; + + // programming PMC: + // ldi PMC, imm1 + // ldi PMC, imm2 + (*pc)++; + pmcv = imm | (PROGRAM((*pc)++) << 16); + known_regs.pmc.v = pmcv; + known_regb |= KRREG_PMC; + dirty_regb |= KRREG_PMC; + known_regs.emu_status |= SSP_PMC_SET; + + // check for possible reg programming + tmpv = PROGRAM(*pc); + if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80) + { + int is_write = (tmpv & 0xff8f) == 0x80; + int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7); + if (reg > 4) tr_unhandled(); + if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled(); + known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv; + known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); + dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); + known_regs.emu_status &= ~SSP_PMC_SET; + (*pc)++; + return 5; + } + + tr_unhandled(); + return 4; +} + +static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 }; + +static int tr_detect_pm0_block(unsigned int op, int *pc, int imm) +{ + // ldi ST, 0 + // ldi PM0, 0 + // ldi PM0, 0 + // ldi ST, 60h + unsigned short *pp; + if (op != 0x0840 || imm != 0) return 0; + pp = PROGRAM_P(*pc); + if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0; + + EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK + EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600 + hostreg_sspreg_changed(SSP_ST); + known_regs.gr[SSP_ST].h = 0x60; + known_regb |= 1 << SSP_ST; + dirty_regb &= ~KRREG_ST; + (*pc) += 3*2; + return 4*2; +} + +static int tr_detect_rotate(unsigned int op, int *pc, int imm) +{ + // @ 3DA2 and 426A + // ld PMC, (r3|00) + // ld (r3|00), PMC + // ld -, AL + if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0; + + tr_bank_read(0); + EOP_MOV_REG_LSL(0, 0, 4); + EOP_ORR_REG_LSR(0, 0, 0, 16); + tr_bank_write(0); + (*pc) += 2; + return 3; +} + +// ----------------------------------------------------- static int translate_op(unsigned int op, int *pc, int imm) { - u32 tmpv, tmpv2; + u32 tmpv, tmpv2, tmpv3; int ret = 0; known_regs.gr[SSP_PC].h = *pc; @@ -1050,16 +1639,17 @@ static int translate_op(unsigned int op, int *pc, int imm) if (op == 0) { ret++; break; } // nop tmpv = op & 0xf; // src tmpv2 = (op >> 4) & 0xf; // dst - if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO + //if (tmpv2 >= 8) return -1; // TODO if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P tr_flush_dirty_P(); EOP_MOV_REG_SIMPLE(5, 10); - hostreg_sspreg_changed(SSP_A); \ + hostreg_sspreg_changed(SSP_A); known_regb &= ~(KRREG_A|KRREG_AL); ret++; break; } - tr_read_funcs[tmpv](); + tr_read_funcs[tmpv](op); tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1); + if (tmpv2 == SSP_PC) ret |= 0x10000; ret++; break; // ld d, (ri) @@ -1068,20 +1658,22 @@ static int translate_op(unsigned int op, int *pc, int imm) int r = (op&3) | ((op>>6)&4); int mod = (op>>2)&3; tmpv = (op >> 4) & 0xf; // dst + ret = tr_detect_rotate(op, pc, imm); + if (ret > 0) break; if (tmpv >= 8) return -1; // TODO if (tmpv != 0) tr_rX_read(r, mod); else tr_ptrr_mod(r, mod, 1, 1); tr_write_funcs[tmpv](-1); + if (tmpv == SSP_PC) ret |= 0x10000; ret++; break; } // ld (ri), s case 0x02: tmpv = (op >> 4) & 0xf; // src - if (tmpv >= 8) return -1; // TODO - tr_read_funcs[tmpv](); - tr_rX_write1(op); + tr_read_funcs[tmpv](op); + tr_rX_write(op); ret++; break; // ld a, adr @@ -1092,89 +1684,38 @@ static int translate_op(unsigned int op, int *pc, int imm) // ldi d, imm case 0x04: - tmpv = (op & 0xf0) >> 4; + tmpv = (op & 0xf0) >> 4; // dst + ret = tr_detect_pm0_block(op, pc, imm); + if (ret > 0) break; if (tmpv < 8) { tr_mov16(0, imm); tr_write_funcs[tmpv](imm); ret += 2; break; } - else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4) - { - // programming PMC.. - (*pc)++; - tmpv = imm | (PROGRAM((*pc)++) << 16); - ret += 2; - emit_mov_const(A_COND_AL, 0, tmpv); - EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status - EOP_STR_IMM(0,7,0x400+14*4); // PMC - // reads on fe06, fe08; next op is ld -, - if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0) - { - int flag = (tmpv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08; - tr_flush_dirty_ST(); - EOP_LDR_IMM(0,7,0x490); // dram_ptr - EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00 - EOP_LDRH_IMM(0,0,(tmpv == 0x187f03) ? 6 : 8); // ldrh r0, [r0, #8] - EOP_TST_REG_SIMPLE(0,0); - EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024 - EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08 - } - EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET - EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status - hostreg_r[0] = hostreg_r[1] = -1; - ret += 2; break; - } - else - return -1; /* TODO.. */ + ret = tr_detect_set_pm(op, pc, imm); + if (ret > 0) break; + if (tmpv == SSP_PC) ret |= 0x10000; + return -1; /* TODO.. */ // ld d, ((ri)) - case 0x05: { - int r; - r = (op&3) | ((op>>6)&4); // src + case 0x05: tmpv2 = (op >> 4) & 0xf; // dst if (tmpv2 >= 8) return -1; // TODO - - if ((r&3) == 3) { - tr_bank_read((op&0x100) | ((op>>2)&3)); - } else if (known_regb & (1 << (r+8))) { - tr_bank_read((op&0x100) | known_regs.r[r]); - } else { - int reg = (r < 4) ? 8 : 9; - int ror = ((4 - (r&3))*8) & 0x1f; - EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, - if (r >= 4) - EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<>2)&3)); - } else if (known_regb & (1 << (r+8))) { - tr_bank_write((op&0x100) | known_regs.r[r]); - } else { - EOP_STRH_SIMPLE(0,1); // strh r0, [r1] - hostreg_r[1] = -1; - } - EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2] - hostreg_r[0] = hostreg_r[2] = -1; + tr_rX_read2(op); tr_write_funcs[tmpv2](-1); - ret += 3; break; /* should certainly take > 1 */ - } + if (tmpv2 == SSP_PC) ret |= 0x10000; + ret += 3; break; // ldi (ri), imm case 0x06: tr_mov16(0, imm); - tr_rX_write1(op); + tr_rX_write(op); ret += 2; break; // ld adr, a case 0x07: - tr_A_to_r0(); + tr_A_to_r0(op); tr_bank_write(op&0x1ff); ret++; break; @@ -1204,7 +1745,6 @@ static int translate_op(unsigned int op, int *pc, int imm) int r; r = (op&3) | ((op>>6)&4); // dst tmpv = (op >> 4) & 0xf; // src - if (tmpv >= 8) tr_unhandled(); if ((r&3) == 3) tr_unhandled(); if (known_regb & (1 << tmpv)) { @@ -1214,7 +1754,7 @@ static int translate_op(unsigned int op, int *pc, int imm) } else { int reg = (r < 4) ? 8 : 9; int ror = ((4 - (r&3))*8) & 0x1f; - tr_read_funcs[tmpv](); + tr_read_funcs[tmpv](op); EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl @@ -1254,6 +1794,7 @@ static int translate_op(unsigned int op, int *pc, int imm) tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); } tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); + ret |= 0x10000; ret += 2; break; } @@ -1262,12 +1803,13 @@ static int translate_op(unsigned int op, int *pc, int imm) tmpv2 = (op >> 4) & 0xf; // dst if (tmpv2 >= 8) return -1; // TODO - tr_A_to_r0(); + tr_A_to_r0(op); EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0] hostreg_r[0] = hostreg_r[1] = -1; tr_write_funcs[tmpv2](-1); + if (tmpv2 == SSP_PC) ret |= 0x10000; ret += 3; break; // bra cond, addr @@ -1278,6 +1820,7 @@ static int translate_op(unsigned int op, int *pc, int imm) tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); } tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); + ret |= 0x10000; ret += 2; break; // mod cond, op @@ -1307,35 +1850,170 @@ static int translate_op(unsigned int op, int *pc, int imm) known_regb &= ~(KRREG_A|KRREG_AL); ret += tmpv; break; } -/* + // mpys? case 0x1b: - read_P(); // update P - rA32 -= rP.v; // maybe only upper word? - UPD_ACC_ZN // there checking flags after this - rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?) - rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj - break; + tr_flush_dirty_P(); + tr_mac_load_XY(op); + tr_make_dirty_ST(); + EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL); + dirty_regb |= KRREG_ST; + ret++; break; // mpya (rj), (ri), b case 0x4b: - read_P(); // update P - rA32 += rP.v; // confirmed to be 32bit - UPD_ACC_ZN // ? - rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?) - rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj - break; + tr_flush_dirty_P(); + tr_mac_load_XY(op); + tr_make_dirty_ST(); + EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL); + dirty_regb |= KRREG_ST; + ret++; break; // mld (rj), (ri), b case 0x5b: - EOP_MOV_IMM(5, 0, 0); // mov r5, #0 - known_regs.r[SSP_A].v = 0; + EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0 + hostreg_sspreg_changed(SSP_A); + known_regs.gr[SSP_A].v = 0; known_regb |= (KRREG_A|KRREG_AL); - EOP_BIC_IMM(6, 6, 0, 0x0f); // bic r6, r6, 0xf // flags - EOP_BIC_IMM(6, 6, 0, 0x04); // bic r6, r6, 4 // set Z - // TODO + dirty_regb |= KRREG_ST; + tr_mac_load_XY(op); + ret++; break; + + // OP a, s + case 0x10: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + tmpv = op & 0xf; // src + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + if (tmpv == SSP_P) { + tr_flush_dirty_P(); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10 + } else if (tmpv == SSP_A) { + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5 + } else { + tr_read_funcs[tmpv](op); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16 + } + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret++; break; + + // OP a, (ri) + case 0x11: + case 0x31: + case 0x41: + case 0x51: + case 0x61: + case 0x71: + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret++; break; + + // OP a, adr + case 0x13: + case 0x33: + case 0x43: + case 0x53: + case 0x63: + case 0x73: + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + tr_bank_read(op&0x1ff); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret++; break; + + // OP a, imm + case 0x14: + case 0x34: + case 0x44: + case 0x54: + case 0x64: + case 0x74: + tmpv = (op & 0xf0) >> 4; + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + tr_mov16(0, imm); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret += 2; break; + + // OP a, ((ri)) + case 0x15: + case 0x35: + case 0x45: + case 0x55: + case 0x65: + case 0x75: + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + tr_rX_read2(op); + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret += 3; break; + + // OP a, ri + case 0x19: + case 0x39: + case 0x49: + case 0x59: + case 0x69: + case 0x79: { + int r; + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + r = (op&3) | ((op>>6)&4); // src + if ((r&3) == 3) tr_unhandled(); + + if (known_regb & (1 << (r+8))) { + EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16 + } else { + int reg = (r < 4) ? 8 : 9; + if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr + EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, + EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 + hostreg_r[0] = -1; + } + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; + ret++; break; + } + + // OP simm + case 0x1c: + case 0x3c: + case 0x4c: + case 0x5c: + case 0x6c: + case 0x7c: + tmpv2 = tr_aop_ssp2arm(op>>13); // op + tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; + EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16 + hostreg_sspreg_changed(SSP_A); + known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); + dirty_regb |= KRREG_ST; ret++; break; -*/ } return ret; @@ -1345,7 +2023,7 @@ static void *translate_block(int pc) { unsigned int op, op1, imm, ccount = 0; unsigned int *block_start; - int ret, ret_prev = -1; + int ret, ret_prev = -1, tpc; // create .pool //*tcache_ptr++ = (u32) in_funcs; // -1 func pool @@ -1354,6 +2032,7 @@ static void *translate_block(int pc) block_start = tcache_ptr; known_regb = 0; dirty_regb = KRREG_P; + known_regs.emu_status = 0; hostreg_clear(); emit_block_prologue(); @@ -1367,12 +2046,15 @@ static void *translate_block(int pc) if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6) imm = PROGRAM(pc++); // immediate + tpc = pc; ret = translate_op(op, &pc, imm); if (ret <= 0) { tr_flush_dirty_prs(); tr_flush_dirty_ST(); + tr_flush_dirty_pmcrs(); + known_regs.emu_status = 0; emit_mov_const(A_COND_AL, 0, op); @@ -1397,18 +2079,17 @@ static void *translate_block(int pc) known_regb = 0; } else - ccount += ret; - - if (op1 == 0x24 || op1 == 0x26 || // call, bra - ((op1 == 0 || op1 == 1 || op1 == 4 || op1 == 5 || op1 == 9 || op1 == 0x25) && - (op & 0xf0) == 0x60)) { // ld PC - break; + { + ccount += ret & 0xffff; + if (ret & 0x10000) break; } + ret_prev = ret; } tr_flush_dirty_prs(); tr_flush_dirty_ST(); + tr_flush_dirty_pmcrs(); emit_block_epilogue(ccount + 1); *tcache_ptr++ = 0xffffffff; // end of block //printf(" %i inst\n", icount); @@ -1451,6 +2132,11 @@ int ssp1601_dyn_startup(void) tcache_ptr = tcache; *tcache_ptr++ = 0xffffffff; +#ifdef ARM + // hle'd blocks + block_table[0x400] = (void *) ssp_hle_800; +#endif + // TODO: rm { static unsigned short dummy = 0; @@ -1463,9 +2149,10 @@ PC = &dummy; void ssp1601_dyn_reset(ssp1601_t *ssp) { ssp1601_reset_local(ssp); - ssp->ptr_rom = (unsigned int) Pico.rom; - ssp->ptr_iram_rom = (unsigned int) svp->iram_rom; - ssp->ptr_dram = (unsigned int) svp->dram; + ssp->drc.ptr_rom = (unsigned int) Pico.rom; + ssp->drc.ptr_iram_rom = (unsigned int) svp->iram_rom; + ssp->drc.ptr_dram = (unsigned int) svp->dram; + ssp->drc.iram_dirty = 0; } void ssp1601_dyn_run(int cycles) @@ -1482,9 +2169,9 @@ void ssp1601_dyn_run(int cycles) int (*trans_entry)(void); if (rPC < 0x800/2) { - if (iram_dirty) { + if (ssp->drc.iram_dirty) { iram_context = get_iram_context(); - iram_dirty--; + ssp->drc.iram_dirty--; } if (block_table_iram[iram_context][rPC] == NULL) block_table_iram[iram_context][rPC] = translate_block(rPC);