X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2Fcarthw%2Fsvp%2Fcompiler.c;h=cfaa8a76e6171f7eb69986a9ea226fc68b56b975;hb=89fea1e97270502440365bfd2f4aa34111847682;hp=577e69927b1916b0c8d58f2109fee43b0a699c4c;hpb=b9c1d0129a0842bb545dd30cef73aa975acbb1ac;p=picodrive.git

diff --git a/Pico/carthw/svp/compiler.c b/Pico/carthw/svp/compiler.c
index 577e699..cfaa8a7 100644
--- a/Pico/carthw/svp/compiler.c
+++ b/Pico/carthw/svp/compiler.c
@@ -8,12 +8,11 @@ static unsigned int *block_table[0x5090/2];
 static unsigned int *block_table_iram[15][0x800/2];
 static unsigned int *tcache_ptr = NULL;
 
-static int had_jump = 0;
 static int nblocks = 0;
 static int iram_context = 0;
 
 #ifndef ARM
-#define DUMP_BLOCK 0x84a
+#define DUMP_BLOCK 0x3516
 unsigned int tcache[512*1024];
 void regfile_load(void){}
 void regfile_store(void){}
@@ -25,7 +24,7 @@ void regfile_store(void){}
 
 #define GET_PC() rPC
 #define GET_PPC_OFFS() (GET_PC()*2 - 2)
-#define SET_PC(d) { had_jump = 1; rPC = d; }		/* must return to dispatcher after this */
+#define SET_PC(d) { rPC = d; }		/* must return to dispatcher after this */
 //#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
 //#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
 //#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
@@ -534,27 +533,34 @@ static struct
 {
 	ssp_reg_t gr[8];
 	unsigned char r[8];
-} const_regs;
-
-#define CRREG_X     (1 << SSP_X)
-#define CRREG_Y     (1 << SSP_Y)
-#define CRREG_A     (1 << SSP_A)	/* AH only */
-#define CRREG_ST    (1 << SSP_ST)
-#define CRREG_STACK (1 << SSP_STACK)
-#define CRREG_PC    (1 << SSP_PC)
-#define CRREG_P     (1 << SSP_P)
-#define CRREG_PR0   (1 << 8)
-#define CRREG_PR4   (1 << 12)
-#define CRREG_AL    (1 << 16)
-
-static u32 const_regb = 0;		/* bitfield of known register values */
-static u32 dirty_regb = 0;		/* known vals, which need to be flushed (only r0-r7) */
+} known_regs;
+
+#define KRREG_X     (1 << SSP_X)
+#define KRREG_Y     (1 << SSP_Y)
+#define KRREG_A     (1 << SSP_A)	/* AH only */
+#define KRREG_ST    (1 << SSP_ST)
+#define KRREG_STACK (1 << SSP_STACK)
+#define KRREG_PC    (1 << SSP_PC)
+#define KRREG_P     (1 << SSP_P)
+#define KRREG_PR0   (1 << 8)
+#define KRREG_PR4   (1 << 12)
+#define KRREG_AL    (1 << 16)
+
+/* bitfield of known register values */
+static u32 known_regb = 0;
+
+/* known vals, which need to be flushed
+ * (only ST, P, r0-r7)
+ * ST means flags are being held in ARM PSR
+ * P means that it needs to be recalculated
+ */
+static u32 dirty_regb = 0;
 
 /* known values of host regs.
- * -1          - unknown
- * 00000-0ffff - 16bit value
- * 10000-1ffff - base reg (r7) + 16bit val
- * 20000       - means reg (low) eq AH
+ * -1            - unknown
+ * 000000-00ffff - 16bit value
+ * 100000-10ffff - base reg (r7) + 16bit val
+ * 0r0000        - means reg (low) eq gr[r].h
  */
 static int hostreg_r[4];
 
@@ -565,34 +571,57 @@ static void hostreg_clear(void)
 		hostreg_r[i] = -1;
 }
 
+// TODO
 /*static*/ void hostreg_ah_changed(void)
 {
 	int i;
 	for (i = 0; i < 4; i++)
-		if (hostreg_r[i] == 0x20000) hostreg_r[i] = -1;
+		if (hostreg_r[i] == (SSP_A<<16)) hostreg_r[i] = -1;
 }
 
 
 #define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
 
-/* load 16bit val into host reg r0-r3. Nothing is trashed */
-static void tr_mov16(int r, int val)
+/* update P, if needed. Trashes r1 */
+static void tr_flush_dirty_P(void)
 {
-	if (hostreg_r[r] != val) {
-		emit_mov_const(r, val);
-		hostreg_r[r] = val;
+	// TODO: const regs
+	if (!(dirty_regb & KRREG_P)) return;
+	EOP_MOV_REG_ASR(10, 4, 16);		// mov  r10, r4, asr #16
+	EOP_MOV_REG_LSL( 1, 4, 16);		// mov  r1,  r4, lsl #16
+	EOP_MOV_REG_ASR( 1, 1, 15);		// mov  r1,  r1, asr #15
+	EOP_MUL(10, 1, 10);			// mul  r10, r1, r10
+	dirty_regb &= ~KRREG_P;
+}
+
+/* write dirty pr to host reg. Nothing is trashed */
+static void tr_flush_dirty_pr(int r)
+{
+	int ror = 0, reg;
+	
+	if (!(dirty_regb & (1 << (r+8)))) return;
+
+	switch (r&3) {
+		case 0: ror =    0; break;
+		case 1: ror = 24/2; break;
+		case 2: ror = 16/2; break;
 	}
+	reg = (r < 4) ? 8 : 9;
+	EOP_BIC_IMM(reg,reg,ror,0xff);
+	if (known_regs.r[r] != 0)
+		EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
+	dirty_regb &= ~(1 << (r+8));
 }
 
-/* write dirty r0-r7 to host regs. Nothing is trashed */
-static void tr_flush_dirty(void)
+/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
+static void tr_flush_dirty_prs(void)
 {
 	int i, ror = 0, reg;
-	dirty_regb >>= 8;
+	int dirty = dirty_regb >> 8;
 	/* r0-r7 */
-	for (i = 0; dirty_regb && i < 8; i++, dirty_regb >>= 1)
+	for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 	{
-		if (!(dirty_regb&1)) continue;
+		if (!(dirty&1)) continue;
 		switch (i&3) {
 			case 0: ror =    0; break;
 			case 1: ror = 24/2; break;
@@ -600,27 +629,57 @@ static void tr_flush_dirty(void)
 		}
 		reg = (i < 4) ? 8 : 9;
 		EOP_BIC_IMM(reg,reg,ror,0xff);
-		if (const_regs.r[i] != 0)
-			EOP_ORR_IMM(reg,reg,ror,const_regs.r[i]);
+		if (known_regs.r[i] != 0)
+			EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 	}
+	dirty_regb &= ~0xff00;
+}
+
+/* write dirty pr and "forget" it. Nothing is trashed. */
+static void tr_release_pr(int r)
+{
+	tr_flush_dirty_pr(r);
+	known_regb &= ~(1 << (r+8));
+}
+
+/* fush ARM PSR to r6. Trashes r0 */
+static void tr_flush_dirty_ST(void)
+{
+	if (!(dirty_regb & KRREG_ST)) return;
+	EOP_BIC_IMM(6,6,0,0x0f);
+	EOP_MRS(0);
+	EOP_ORR_REG_LSR(6,6,0,28);
+	dirty_regb &= ~KRREG_ST;
+	hostreg_r[0] = -1;
 }
 
-/* read bank word to r0 (MSW may contain trash). Thrashes r1. */
+/* load 16bit val into host reg r0-r3. Nothing is trashed */
+static void tr_mov16(int r, int val)
+{
+	if (hostreg_r[r] != val) {
+		emit_mov_const(A_COND_AL, r, val);
+		hostreg_r[r] = val;
+	}
+}
+
+static void tr_mov16_cond(int cond, int r, int val)
+{
+	emit_mov_const(cond, r, val);
+	hostreg_r[r] = -1;
+}
+
+/* read bank word to r0. Thrashes r1. */
 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 {
-	if (addr&1) {
-		int breg = 7;
-		if (addr > 0x7f) {
-			if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
-				EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);	// add  r1, r7, ((op&0x180)<<1)
-				hostreg_r[1] = 0x10000|((addr&0x180)<<1);
-			}
-			breg = 1;
+	int breg = 7;
+	if (addr > 0x7f) {
+		if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
+			EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);	// add  r1, r7, ((op&0x180)<<1)
+			hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 		}
-		EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);	// ldrh r0, [r1, (op&0x7f)<<1]
-	} else {
-		EOP_LDR_IMM(0,7,(addr&0x1ff)<<1);	// ldr  r0, [r1, (op&0x1ff)<<1]
+		breg = 1;
 	}
+	EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);	// ldrh r0, [r1, (op&0x7f)<<1]
 	hostreg_r[0] = -1;
 }
 
@@ -629,46 +688,157 @@ static void tr_bank_write(int addr)
 {
 	int breg = 7;
 	if (addr > 0x7f) {
-		if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
+		if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 			EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);	// add  r1, r7, ((op&0x180)<<1)
-			hostreg_r[1] = 0x10000|((addr&0x180)<<1);
+			hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 		}
 		breg = 1;
 	}
 	EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);		// strh r0, [r1, (op&0x7f)<<1]
 }
 
-/* handle RAM bank pointer modifiers. Nothing is trashed. */
-static void tr_ptrr_mod(int r, int mod, int need_modulo)
+/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
+static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 {
-	int modulo = -1, modulo_shift = -1;	/* unknown */
+	int modulo_shift = -1;	/* unknown */
 
 	if (mod == 0) return;
 
 	if (!need_modulo || mod == 1) // +!
 		modulo_shift = 8;
-	else if (need_modulo && (const_regb & CRREG_ST)) {
-		modulo_shift = const_regs.gr[SSP_ST].h & 7;
+	else if (need_modulo && (known_regb & KRREG_ST)) {
+		modulo_shift = known_regs.gr[SSP_ST].h & 7;
 		if (modulo_shift == 0) modulo_shift = 8;
 	}
 
-	if (mod > 1 && modulo_shift == -1) { printf("need var modulo\n"); exit(1); }
-	modulo = (1 << modulo_shift) - 1;
-
-	if (const_regb & (1 << (r + 8))) {
+	if (modulo_shift == -1)
+	{
+		int reg = (r < 4) ? 8 : 9;
+		tr_release_pr(r);
+		tr_flush_dirty_ST();
+		EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70);	// ands  r1, r6, #0x70
+		EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
+		EOP_MOV_REG_LSR(1, 1, 4);		// mov r1, r1, lsr #4
+		EOP_RSB_IMM(2, 1, 0, 8);		// rsb r1, r1, #8
+		EOP_MOV_IMM(3, 8/2, count);		// mov r3, #0x01000000
+		if (r&3)
+			EOP_ADD_IMM(1, 1, 0, (r&3)*8);	// add r1, r1, #(r&3)*8
+		EOP_MOV_REG2_ROR(reg,reg,1);		// mov reg, reg, ror r1
 		if (mod == 2)
-		     const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] - 1) & modulo);
-		else const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] + 1) & modulo);
-	} else {
+		     EOP_SUB_REG2_LSL(reg,reg,3,2);	// sub reg, reg, #0x01000000 << r2
+		else EOP_ADD_REG2_LSL(reg,reg,3,2);
+		EOP_RSB_IMM(1, 1, 0, 32);		// rsb r1, r1, #32
+		EOP_MOV_REG2_ROR(reg,reg,1);		// mov reg, reg, ror r1
+		hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
+	}
+	else if (known_regb & (1 << (r + 8)))
+	{
+		int modulo = (1 << modulo_shift) - 1;
+		if (mod == 2)
+		     known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
+		else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
+	}
+	else
+	{
 		int reg = (r < 4) ? 8 : 9;
 		int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 		EOP_MOV_REG_ROR(reg,reg,ror);
 		// {add|sub} reg, reg, #1<<shift
-		EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
+		EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 		EOP_MOV_REG_ROR(reg,reg,32-ror);
 	}
 }
 
+/* handle writes r0 to (rX). Trashes r1.
+ * fortunately we can ignore modulo increment modes for writes. */
+static void tr_rX_write1(int op)
+{
+	if ((op&3) == 3)
+	{
+		int mod = (op>>2) & 3; // direct addressing
+		tr_bank_write((op & 0x100) + mod);
+	}
+	else
+	{
+		int r = (op&3) | ((op>>6)&4);
+		if (known_regb & (1 << (r + 8))) {
+			tr_bank_write((op&0x100) | known_regs.r[r]);
+		} else {
+			int reg = (r < 4) ? 8 : 9;
+			int ror = ((4 - (r&3))*8) & 0x1f;
+			EOP_AND_IMM(1,reg,ror/2,0xff);			// and r1, r{7,8}, <mask>
+			if (r >= 4)
+				EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);		// orr r1, r1, 1<<shift
+			if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);	// add r1, r7, r1, lsr #lsr
+			else     EOP_ADD_REG_LSL(1,7,1,1);
+			EOP_STRH_SIMPLE(0,1);				// strh r0, [r1]
+			hostreg_r[1] = -1;
+		}
+		tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
+	}
+}
+
+/* read (rX) to r0. Trashes r1-r3. */
+static void tr_rX_read(int r, int mod)
+{
+	if ((r&3) == 3)
+	{
+		tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
+	}
+	else
+	{
+		if (known_regb & (1 << (r + 8))) {
+			tr_bank_write(((r << 6) & 0x100) | known_regs.r[r]);
+		} else {
+			int reg = (r < 4) ? 8 : 9;
+			int ror = ((4 - (r&3))*8) & 0x1f;
+			EOP_AND_IMM(1,reg,ror/2,0xff);			// and r1, r{7,8}, <mask>
+			if (r >= 4)
+				EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);		// orr r1, r1, 1<<shift
+			if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);	// add r1, r7, r1, lsr #lsr
+			else     EOP_ADD_REG_LSL(1,7,1,1);
+			EOP_LDRH_SIMPLE(0,1);				// ldrh r0, [r1]
+			hostreg_r[1] = -1;
+		}
+		tr_ptrr_mod(r, mod, 1, 1);
+	}
+}
+
+
+/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
+static int tr_cond_check(int op)
+{
+	int f = op & 0x100;
+	switch (op&0xf0) {
+		case 0x00: return A_COND_AL;	/* always true */
+		case 0x50:			/* Z matches f(?) bit */
+			if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
+			EOP_TST_IMM(6, 0, 4);
+			return f ? A_COND_NE : A_COND_EQ;
+		case 0x70:			/* N matches f(?) bit */
+			if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
+			EOP_TST_IMM(6, 0, 8);
+			return f ? A_COND_NE : A_COND_EQ;
+		default:
+			printf("unimplemented cond?\n");
+			exit(1);
+			return 0;
+	}
+}
+
+static int tr_neg_cond(int cond)
+{
+	switch (cond) {
+		case A_COND_AL: printf("neg for AL?\n"); exit(1);
+		case A_COND_EQ: return A_COND_NE;
+		case A_COND_NE: return A_COND_EQ;
+		case A_COND_MI: return A_COND_PL;
+		case A_COND_PL: return A_COND_MI;
+		default:        printf("bad cond for neg\n"); exit(1);
+	}
+	return 0;
+}
+
 //	SSP_GR0, SSP_X,     SSP_Y,   SSP_A,
 //	SSP_ST,  SSP_STACK, SSP_PC,  SSP_P,
 //@ r4:  XXYY
@@ -677,10 +847,87 @@ static void tr_ptrr_mod(int r, int mod, int need_modulo)
 //@ r7:  SSP context
 //@ r10: P
 
+// read general reg to r0. Trashes r1
+static void tr_GR0_to_r0(void)
+{
+	tr_mov16(0, 0xffff);
+}
+
+static void tr_X_to_r0(void)
+{
+	if (hostreg_r[0] != (SSP_X<<16)) {
+		EOP_MOV_REG_LSR(0, 4, 16);	// mov  r0, r4, lsr #16
+		hostreg_r[0] = SSP_X<<16;
+	}
+}
+
+static void tr_Y_to_r0(void)
+{
+	// TODO..
+	if (hostreg_r[0] != (SSP_Y<<16)) {
+		EOP_MOV_REG_SIMPLE(0, 4);	// mov  r0, r4
+		hostreg_r[0] = SSP_Y<<16;
+	}
+}
+
+static void tr_A_to_r0(void)
+{
+	if (hostreg_r[0] != (SSP_A<<16)) {
+		EOP_MOV_REG_LSR(0, 5, 16);	// mov  r0, r5, lsr #16  @ AH
+		hostreg_r[0] = SSP_A<<16;
+	}
+}
+
+static void tr_ST_to_r0(void)
+{
+	// VR doesn't need much accuracy here..
+	EOP_MOV_REG_LSR(0, 6, 4);		// mov  r0, r6, lsr #4
+	EOP_AND_IMM(0, 0, 0, 0x67);		// and  r0, r0, #0x67
+	hostreg_r[0] = -1;
+}
+
+static void tr_STACK_to_r0(void)
+{
+	// 448
+	EOP_SUB_IMM(6, 6,  8/2, 0x20);		// sub  r6, r6, #1<<29
+	EOP_ADD_IMM(1, 7, 24/2, 0x04);		// add  r1, r7, 0x400
+	EOP_ADD_IMM(1, 1, 0, 0x48);		// add  r1, r1, 0x048
+	EOP_ADD_REG_LSR(1, 1, 6, 28);		// add  r1, r1, r6, lsr #28
+	EOP_LDRH_SIMPLE(0, 1);			// ldrh r0, [r1]
+	hostreg_r[0] = hostreg_r[1] = -1;
+}
+
+static void tr_PC_to_r0(void)
+{
+	tr_mov16(0, known_regs.gr[SSP_PC].h);
+}
+
+static void tr_P_to_r0(void)
+{
+	tr_flush_dirty_P();
+	EOP_MOV_REG_LSR(0, 10, 16);		// mov  r0, r10, lsr #16
+	hostreg_r[0] = -1;
+}
+
+typedef void (tr_read_func)(void);
+
+static tr_read_func *tr_read_funcs[8] =
+{
+	tr_GR0_to_r0,
+	tr_X_to_r0,
+	tr_Y_to_r0,
+	tr_A_to_r0,
+	tr_ST_to_r0,
+	tr_STACK_to_r0,
+	tr_PC_to_r0,
+	tr_P_to_r0
+};
+
+
 // write r0 to general reg handlers. Trashes r1
-static void tr_r0_unhandled(void)
+static void tr_unhandled(void)
 {
-	printf("unhandled\n");
+	printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 	exit(1);
 }
 
@@ -694,6 +941,8 @@ static void tr_r0_to_X(void)
 	EOP_MOV_REG_LSL(4, 4, 16);		// mov  r4, r4, lsl #16
 	EOP_MOV_REG_LSR(4, 4, 16);		// mov  r4, r4, lsr #16
 	EOP_ORR_REG_LSL(4, 4, 0, 16);		// orr  r4, r4, r0, lsl #16
+	dirty_regb |= KRREG_P;	// touching X or Y makes P dirty.
+	hostreg_r[0] = SSP_X<<16;
 }
 
 static void tr_r0_to_Y(void)
@@ -701,14 +950,16 @@ static void tr_r0_to_Y(void)
 	EOP_MOV_REG_LSR(4, 4, 16);		// mov  r4, r4, lsr #16
 	EOP_ORR_REG_LSL(4, 4, 0, 16);		// orr  r4, r4, r0, lsl #16
 	EOP_MOV_REG_ROR(4, 4, 16);		// mov  r4, r4, ror #16
+	dirty_regb |= KRREG_P;
+	hostreg_r[0] = SSP_Y<<16;
 }
 
 static void tr_r0_to_A(void)
 {
 	EOP_MOV_REG_LSL(5, 5, 16);		// mov  r5, r5, lsl #16
-	EOP_MOV_REG_LSR(5, 5, 16);		// mov  r5, r5, lsl #16  @ AL
+	EOP_MOV_REG_LSR(5, 5, 16);		// mov  r5, r5, lsr #16  @ AL
 	EOP_ORR_REG_LSL(5, 5, 0, 16);		// orr  r5, r5, r0, lsl #16
-	hostreg_r[0] = 0x20000;
+	hostreg_r[0] = SSP_A<<16;
 }
 
 static void tr_r0_to_ST(void)
@@ -725,16 +976,16 @@ static void tr_r0_to_STACK(void)
 	// 448
 	EOP_ADD_IMM(1, 7, 24/2, 0x04);		// add  r1, r7, 0x400
 	EOP_ADD_IMM(1, 1, 0, 0x48);		// add  r1, r1, 0x048
-	EOP_ADD_REG_LSR(1, 1, 6, 28);		// add  r1, r1, r6, lsr #26
+	EOP_ADD_REG_LSR(1, 1, 6, 28);		// add  r1, r1, r6, lsr #28
 	EOP_STRH_SIMPLE(0, 1);			// strh r0, [r1]
-	EOP_ADD_IMM(6, 6, 24/2, 0x20);		// add  r6, r6, #1<<29
+	EOP_ADD_IMM(6, 6,  8/2, 0x20);		// add  r6, r6, #1<<29
 	hostreg_r[1] = -1;
 }
 
 static void tr_r0_to_PC(void)
 {
 	EOP_MOV_REG_LSL(1, 0, 16);		// mov  r1, r0, lsl #16
-	EOP_STR_IMM(0,7,0x400+6*4);		// str r0, [r7, #(0x400+6*8)]
+	EOP_STR_IMM(1,7,0x400+6*4);		// str  r1, [r7, #(0x400+6*8)]
 	hostreg_r[1] = -1;
 }
 
@@ -749,28 +1000,69 @@ static tr_write_func *tr_write_funcs[8] =
 	tr_r0_to_ST,
 	tr_r0_to_STACK,
 	tr_r0_to_PC,
-	tr_r0_unhandled
+	tr_unhandled
 };
 
 
 static int translate_op(unsigned int op, int *pc, int imm)
 {
-	u32 tmpv;
+	u32 tmpv, tmpv2;
 	int ret = 0;
+	known_regs.gr[SSP_PC].h = *pc;
 
 	switch (op >> 9)
 	{
 		// ld d, s
 		case 0x00:
 			if (op == 0) { ret++; break; } // nop
-			break;
+			tmpv  = op & 0xf; // src
+			tmpv2 = (op >> 4) & 0xf; // dst
+			if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO
+			if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
+				tr_flush_dirty_P();
+				EOP_MOV_REG_SIMPLE(5, 10);
+				known_regb &= ~(KRREG_A|KRREG_AL);
+				ret++; break;
+			}
+			tr_read_funcs[tmpv]();
+			tr_write_funcs[tmpv2]();
+			if (known_regb & (1 << tmpv)) {
+				known_regs.gr[tmpv2].h = known_regs.gr[tmpv].h;
+				known_regb |=   1 << tmpv2;
+			} else
+				known_regb &= ~(1 << tmpv2);
+			ret++; break;
+
+		// ld d, (ri)
+		// TODO: test
+		case 0x01: {
+			// tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+			int r = (op&3) | ((op>>6)&4);
+			int mod = (op>>2)&3;
+			tmpv = (op >> 4) & 0xf; // dst
+			if (tmpv >= 8) return -1; // TODO
+			if (tmpv != 0)
+			     tr_rX_read(r, mod);
+			else tr_ptrr_mod(r, mod, 1, 1);
+			tr_write_funcs[tmpv]();
+			known_regb &= ~(1 << tmpv);
+			ret++; break;
+		}
+
+		// ld (ri), s
+		case 0x02:
+			tmpv = (op >> 4) & 0xf; // src
+			if (tmpv >= 8) return -1; // TODO
+			tr_read_funcs[tmpv]();
+			tr_rX_write1(op);
+			ret++; break;
 
 		// ld a, adr
 		case 0x03:
 			tr_bank_read(op&0x1ff);
 			tr_r0_to_A();
-			const_regb &= ~CRREG_A;
-			hostreg_r[0] = 0x20000;
+			known_regb &= ~KRREG_A;
+			hostreg_r[0] = SSP_A<<16;
 			ret++; break;
 
 		// ldi d, imm
@@ -780,26 +1072,30 @@ static int translate_op(unsigned int op, int *pc, int imm)
 			{
 				tr_mov16(0, imm);
 				tr_write_funcs[tmpv]();
-				const_regs.gr[tmpv].h = imm;
-				const_regb |= 1 << tmpv;
-				ret++; break;
+				known_regs.gr[tmpv].h = imm;
+				known_regb |= 1 << tmpv;
+				ret += 2; break;
 			}
 			else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
 			{
 				// programming PMC..
 				(*pc)++;
 				tmpv = imm | (PROGRAM((*pc)++) << 16);
-				emit_mov_const(0, tmpv);
+				ret += 2;
+				emit_mov_const(A_COND_AL, 0, tmpv);
 				EOP_LDR_IMM(1,7,0x484);		// ldr r0, [r7, #0x484] // emu_status
 				EOP_STR_IMM(0,7,0x400+14*4);	// PMC
-				// TODO: do this only on reads
-				if (tmpv == 0x187f04) { // fe08
+				// reads on fe06, fe08; next op is ld -,
+				if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
+				{
+					int flag = (tmpv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
+					tr_flush_dirty_ST();
 					EOP_LDR_IMM(0,7,0x490); // dram_ptr
 					EOP_ADD_IMM(0,0,24/2,0xfe);	// add  r0, r0, #0xfe00
 					EOP_LDRH_IMM(0,0,8);		// ldrh r0, [r0, #8]
 					EOP_TST_REG_SIMPLE(0,0);
-					EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
-					EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,SSP_WAIT_30FE08>>8); // orr r1, r1, #SSP_WAIT_30FE08
+					EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1);	// add r11, r11, #1024
+					EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8);	// orr r1, r1, #SSP_WAIT_30FE08
 				}
 				EOP_ORR_IMM(1,1,0,SSP_PMC_SET);		// orr r1, r1, #SSP_PMC_SET
 				EOP_STR_IMM(1,7,0x484);			// str r1, [r7, #0x484] // emu_status
@@ -809,60 +1105,205 @@ static int translate_op(unsigned int op, int *pc, int imm)
 			else
 				return -1;	/* TODO.. */
 
+		// ld d, ((ri))
+		case 0x05: {
+			int r;
+			r = (op&3) | ((op>>6)&4); // src
+			tmpv2 = (op >> 4) & 0xf;  // dst
+			if (tmpv2 >= 8) return -1; // TODO
+
+			if ((r&3) == 3) {
+				tr_bank_read((op&0x100) | ((op>>2)&3));
+			} else if (known_regb & (1 << (r+8))) {
+				tr_bank_read((op&0x100) | known_regs.r[r]);
+			} else {
+				int reg = (r < 4) ? 8 : 9;
+				int ror = ((4 - (r&3))*8) & 0x1f;
+				EOP_AND_IMM(1,reg,ror/2,0xff);			// and r1, r{7,8}, <mask>
+				if (r >= 4)
+					EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);		// orr r1, r1, 1<<shift
+				if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);	// add r1, r7, r1, lsr #lsr
+				else     EOP_ADD_REG_LSL(1,7,1,1);
+				EOP_LDRH_SIMPLE(0,1);				// ldrh r0, [r1]
+			}
+			EOP_LDR_IMM(2,7,0x48c);					// ptr_iram_rom
+			EOP_ADD_REG_LSL(2,2,0,1);				// add  r2, r2, r0, lsl #1
+			EOP_ADD_IMM(0,0,0,1);					// add  r0, r0, #1
+			if ((r&3) == 3) {
+				tr_bank_write((op&0x100) | ((op>>2)&3));
+			} else if (known_regb & (1 << (r+8))) {
+				tr_bank_write((op&0x100) | known_regs.r[r]);
+			} else {
+				EOP_STRH_SIMPLE(0,1);				// strh r0, [r1]
+				hostreg_r[1] = -1;
+			}
+			EOP_LDRH_SIMPLE(0,2);					// ldrh r0, [r0]
+			hostreg_r[0] = hostreg_r[2] = -1;
+			known_regb &= ~(1 << tmpv2);
+			tr_write_funcs[tmpv2]();
+			ret += 3; break; /* should certainly take > 1 */
+		}
 
 		// ldi (ri), imm
 		case 0x06:
-			// int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
 			tr_mov16(0, imm);
-			if ((op&3) == 3)
-			{
-				tmpv = (op>>2) & 3; // direct addressing
-				if (op & 0x100) {
-					if (hostreg_r[1] != 0x10200) {
-						EOP_ADD_IMM(1,7,30/2,0x200>>2);	// add  r1, r7, 0x200
-						hostreg_r[1] = 0x10200;
-					}
-					EOP_STRH_IMM(0,1,tmpv<<1);	// str  r0, [r1, {0,2,4,6}]
-				} else {
-					EOP_STRH_IMM(0,7,tmpv<<1);	// str  r0, [r7, {0,2,4,6}]
-				}
-			}
-			else
-			{
-				int r = (op&3) | ((op>>6)&4);
-				if (const_regb & (1 << (r + 8))) {
-					tr_bank_write(const_regs.r[r] | ((r < 4) ? 0 : 0x100));
-				} else {
-					int reg = (r < 4) ? 8 : 9;
-					int ror = ((4 - (r&3))*8) & 0x1f;
-					EOP_AND_IMM(1,reg,ror/2,0xff);			// and r1, r{7,8}, <mask>
-					if (r >= 4)
-						EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);		// orr r1, r1, 1<<shift
-					if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);	// add r1, r7, r1, lsr #lsr
-					else     EOP_ADD_REG_LSL(1,7,1,1);
-					EOP_STRH_SIMPLE(0,1);				// strh r0, [r1]
-					hostreg_r[1] = -1;
-				}
-				tr_ptrr_mod(r, (op>>2) & 3, 0);
-			}
-			ret++; break;
+			tr_rX_write1(op);
+			ret += 2; break;
 
 		// ld adr, a
 		case 0x07:
-			if (hostreg_r[0] != 0x20000) {
+			if (hostreg_r[0] != (SSP_A<<16)) {
 				EOP_MOV_REG_LSR(0, 5, 16);		// mov  r0, r5, lsr #16  @ A
-				hostreg_r[0] = 0x20000;
+				hostreg_r[0] = SSP_A<<16;
 			}
 			tr_bank_write(op&0x1ff);
 			ret++; break;
 
+		// ld d, ri
+		case 0x09: {
+			int r;
+			r = (op&3) | ((op>>6)&4); // src
+			tmpv2 = (op >> 4) & 0xf;  // dst
+			if (tmpv2 >= 8) tr_unhandled();
+			if ((r&3) == 3) tr_unhandled();
+
+			if (known_regb & (1 << (r+8))) {
+				tr_mov16(0, known_regs.r[r]);
+				known_regs.gr[tmpv2].h = known_regs.r[r];
+				known_regb |= 1 << tmpv2;
+			} else {
+				int reg = (r < 4) ? 8 : 9;
+				if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);	// mov r0, r{7,8}, lsr #lsr
+				EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);		// and r0, r{7,8}, <mask>
+				hostreg_r[0] = -1;
+				known_regb &= ~(1 << tmpv2);
+			}
+			tr_write_funcs[tmpv2]();
+			ret++; break;
+		}
+
+		// ld ri, s
+		case 0x0a: {
+			int r;
+			r = (op&3) | ((op>>6)&4); // dst
+			tmpv = (op >> 4) & 0xf;   // src
+			if (tmpv >= 8)  tr_unhandled();
+			if ((r&3) == 3) tr_unhandled();
+
+			if (known_regb & (1 << tmpv)) {
+				known_regs.r[r] = known_regs.gr[tmpv].h;
+				known_regb |= 1 << (r + 8);
+				dirty_regb |= 1 << (r + 8);
+			} else {
+				int reg = (r < 4) ? 8 : 9;
+				int ror = ((4 - (r&3))*8) & 0x1f;
+				tr_read_funcs[tmpv]();
+				EOP_BIC_IMM(reg, reg, ror/2, 0xff);		// bic r{7,8}, r{7,8}, <mask>
+				EOP_AND_IMM(0, 0, 0, 0xff);			// and r0, r0, 0xff
+				EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);		// orr r{7,8}, r{7,8}, r0, lsl #lsl
+				hostreg_r[0] = -1;
+				known_regb &= ~(1 << (r+8));
+				dirty_regb &= ~(1 << (r+8));
+			}
+			ret++; break;
+		}
+
 		// ldi ri, simm
 		case 0x0c ... 0x0f:
 			tmpv = (op>>8)&7;
-			const_regs.r[tmpv] = op;
-			const_regb |= 1 << (tmpv + 8);
+			known_regs.r[tmpv] = op;
+			known_regb |= 1 << (tmpv + 8);
 			dirty_regb |= 1 << (tmpv + 8);
 			ret++; break;
+
+		// call cond, addr
+		case 0x24:
+			tr_mov16(0, *pc);
+			tr_r0_to_STACK();
+			tmpv = tr_cond_check(op);
+			tr_mov16_cond(tmpv, 0, imm);
+			if (tmpv != A_COND_AL) {
+				tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+			}
+			tr_r0_to_PC();
+			ret += 2; break;
+
+		// ld d, (a)
+		case 0x25:
+			tmpv2 = (op >> 4) & 0xf;  // dst
+			if (tmpv2 >= 8) return -1; // TODO
+
+			tr_A_to_r0();
+			EOP_LDR_IMM(1,7,0x48c);					// ptr_iram_rom
+			EOP_ADD_REG_LSL(0,1,0,1);				// add  r0, r1, r0, lsl #1
+			EOP_LDRH_SIMPLE(0,0);					// ldrh r0, [r0]
+			hostreg_r[0] = hostreg_r[1] = -1;
+			known_regb &= ~(1 << tmpv2);
+			tr_write_funcs[tmpv2]();
+			ret += 3; break;
+
+		// bra cond, addr
+		case 0x26:
+			tmpv = tr_cond_check(op);
+			tr_mov16_cond(tmpv, 0, imm);
+			if (tmpv != A_COND_AL) {
+				tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+			}
+			tr_r0_to_PC();
+			ret += 2; break;
+
+		// mod cond, op
+		// TODO: test
+		case 0x48: {
+			// check for repeats of this op
+			tmpv = 1; // count
+			while (PROGRAM(*pc) == op && (op & 7) != 6) {
+				(*pc)++; tmpv++;
+			}
+			tmpv2 = tr_cond_check(op);
+			switch (op & 7) {
+				case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
+				case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
+				case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
+				case 7: EOP_C_DOP_IMM(tmpv2,A_OP_EOR,0,5,1,A_AM1_ASR,5);	// eor  r1, r5, r5, asr #31
+					EOP_C_DOP_IMM(tmpv2,A_OP_ADD,1,1,5,A_AM1_LSR,5);	// adds r5, r1, r5, lsr #1
+					hostreg_r[1] = -1; break; // abs
+				default: tr_unhandled();
+			}
+			dirty_regb |= KRREG_ST;
+			ret += tmpv; break;
+		}
+
+
+/*
+		// mpys?
+		case 0x1b:
+			read_P(); // update P
+			rA32 -= rP.v;			// maybe only upper word?
+			UPD_ACC_ZN			// there checking flags after this
+			rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
+			rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+			break;
+
+		// mpya (rj), (ri), b
+		case 0x4b:
+			read_P(); // update P
+			rA32 += rP.v; // confirmed to be 32bit
+			UPD_ACC_ZN // ?
+			rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
+			rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+			break;
+
+		// mld (rj), (ri), b
+		case 0x5b:
+			EOP_MOV_IMM(5, 0, 0);			// mov r5, #0
+			known_regs.r[SSP_A].v = 0;
+			known_regb |= (KRREG_A|KRREG_AL);
+			EOP_BIC_IMM(6, 6, 0, 0x0f);		// bic r6, r6, 0xf // flags
+			EOP_BIC_IMM(6, 6, 0, 0x04);		// bic r6, r6, 4 // set Z
+			// TODO
+			ret++; break;
+*/
 	}
 
 	return ret;
@@ -872,14 +1313,15 @@ static void *translate_block(int pc)
 {
 	unsigned int op, op1, imm, ccount = 0;
 	unsigned int *block_start;
-	int ret;
+	int ret, ret_prev = -1;
 
 	// create .pool
 	//*tcache_ptr++ = (u32) in_funcs;			// -1 func pool
 
 	printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
 	block_start = tcache_ptr;
-	const_regb = dirty_regb = 0;
+	known_regb = 0;
+	dirty_regb = KRREG_P;
 	hostreg_clear();
 
 	emit_block_prologue();
@@ -897,18 +1339,21 @@ static void *translate_block(int pc)
 		ret = translate_op(op, &pc, imm);
 		if (ret <= 0)
 		{
-			tr_flush_dirty();
+			tr_flush_dirty_prs();
+			tr_flush_dirty_ST();
 
-			emit_mov_const(0, op);
+			emit_mov_const(A_COND_AL, 0, op);
 
 			// need immediate?
 			if (imm != (u32)-1)
-				emit_mov_const(1, imm);
+				emit_mov_const(A_COND_AL, 1, imm);
 
 			// dump PC
 			emit_pc_dump(pc);
 
-			emit_interpreter_call(in_funcs[op1]);
+			if (ret_prev > 0) emit_call(regfile_store);
+			emit_call(in_funcs[op1]);
+			emit_call(regfile_load);
 
 			if (in_funcs[op1] == NULL) {
 				printf("NULL func! op=%08x (%02x)\n", op, op1);
@@ -916,6 +1361,8 @@ static void *translate_block(int pc)
 			}
 			ccount++;
 			hostreg_clear();
+			dirty_regb |= KRREG_P;
+			known_regb = 0;
 		}
 		else
 			ccount += ret;
@@ -925,9 +1372,11 @@ static void *translate_block(int pc)
 				(op & 0xf0) == 0x60)) { // ld PC
 			break;
 		}
+		ret_prev = ret;
 	}
 
-	tr_flush_dirty();
+	tr_flush_dirty_prs();
+	tr_flush_dirty_ST();
 	emit_block_epilogue(ccount + 1);
 	*tcache_ptr++ = 0xffffffff; // end of block
 	//printf("  %i inst\n", icount);
@@ -977,9 +1426,9 @@ int ssp1601_dyn_startup(void)
 void ssp1601_dyn_reset(ssp1601_t *ssp)
 {
 	ssp1601_reset_local(ssp);
-	ssp->rom_ptr  = (unsigned int) Pico.rom;
-	ssp->iram_ptr = (unsigned int) svp->iram_rom;
-	ssp->dram_ptr = (unsigned int) svp->dram;
+	ssp->ptr_rom = (unsigned int) Pico.rom;
+	ssp->ptr_iram_rom = (unsigned int) svp->iram_rom;
+	ssp->ptr_dram = (unsigned int) svp->dram;
 }
 
 void ssp1601_dyn_run(int cycles)
@@ -1011,8 +1460,6 @@ void ssp1601_dyn_run(int cycles)
 			trans_entry = (void *) block_table[rPC];
 		}
 
-		had_jump = 0;
-
 		//printf("enter %04x\n", rPC<<1);
 		cycles -= trans_entry();
 		//printf("leave %04x\n", rPC<<1);