X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2Fcarthw%2Fsvp%2Fssp16.c;h=feef99bb41e66bdffe12ad30ca662f5baf27dd6d;hb=71bb1b7bd0186eb056609fec62a134dcaadbffdf;hp=630065c550c00ec3a9080b4717498ef51c70aa5a;hpb=12f0f94d1595ac3bf4a33ded6023197b22572163;p=picodrive.git

diff --git a/Pico/carthw/svp/ssp16.c b/Pico/carthw/svp/ssp16.c
index 630065c..feef99b 100644
--- a/Pico/carthw/svp/ssp16.c
+++ b/Pico/carthw/svp/ssp16.c
@@ -7,6 +7,11 @@
 // For commercial use, separate licencing terms must be obtained.
 
 
+//#define USE_DEBUGGER
+/* detect ops with unimplemented/invalid fields.
+ * Useful for homebrew or if a new VR revision pops up. */
+//#define DO_CHECKS
+
 #include "../../PicoInt.h"
 
 /*
@@ -131,7 +136,7 @@
  * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
  * ar probably invalid.
  *
- * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
+ * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
  * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
  * Samsung's old DSP page claims that).
  * 1 of these 4 modifiers must be used (short form direct addressing?):
@@ -173,25 +178,20 @@
  *
  * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
  * 30fe06 - also sync related.
- * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
- *
- * + figure out if 'op A, P' is 32bit (nearly sure it is)
- * * does mld, mpya load their operands into X and Y?
- * * OP simm
+ * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
  *
- * Assumptions in this code
- *   P is not directly writeable
- *   flags correspond to full 32bit accumulator
- *   only Z and N status flags are emulated (others unused by SVP)
- *   modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
+ * Assumptions and limitations in this code
+ *   only Z and N status flags are emulated (others unused by VR)
+ *   so all condition checks except N and Z are ignored (not used by VR)
+ *   modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
+ *   loop repeat mode when (ri) is destination is ignored
+ *   ops not used by VR are not implemented
  */
 
 #include "../../PicoInt.h"
 
 #define u32 unsigned int
 
-//#define USE_DEBUGGER
-
 // 0
 #define rX     ssp->gr[SSP_X].h
 #define rY     ssp->gr[SSP_Y].h
@@ -214,11 +214,9 @@
 
 #define IJind  (((op>>6)&4)|(op&3))
 
-#ifndef EMBED_INTERPRETER
 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
 #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
-#endif
 
 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
 #define REG_WRITE(r,d) { \
@@ -247,7 +245,7 @@
 	else rST |= (rA32>>16)&SSP_FLAG_N;
 
 // standard cond processing.
-// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
+// again, only Z and N is checked, as VR doesn't seem to use any other conds.
 #define COND_CHECK \
 	switch (op&0xf0) { \
 		case 0x00: cond = 1; break; /* always true */ \
@@ -324,15 +322,46 @@
 	UPD_ACC_ZN
 
 
-#define OP_CHECK32(OP) \
-	if ((op & 0x0f) == SSP_P) { /* A <- P */ \
-	read_P(); /* update P */ \
-	OP(rP.v); \
-	break; \
+#define OP_CHECK32(OP) { \
+	 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
+		read_P(); /* update P */ \
+		OP(rP.v); \
+		break; \
+	} \
+ 	if ((op & 0x0f) == SSP_A) { /* A <- A */ \
+		OP(rA32); \
+		break; \
+	} \
 }
 
 
-static ssp1601_t *ssp = NULL;
+#ifdef DO_CHECKS
+#define CHECK_IMM16()   if (op&0x1ff)    elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_B_SET()   if (op&0x100)    elprintf(EL_ANOMALY, "b set!    %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear!  %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_MOD()     if (op&0x00c)    elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_10f()     if (op&0x10f)    elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_008()     if (op&0x008)    elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_00f()     if (op&0x00f)    elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_0f0()     if (op&0x0f0)    elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_1f0()     if (op&0x1f0)    elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_RPL()     if (rST&7)       elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op,  GET_PPC_OFFS())
+#define CHECK_ST(d)     if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
+#else
+#define CHECK_IMM16()
+#define CHECK_B_SET()
+#define CHECK_B_CLEAR()
+#define CHECK_MOD()
+#define CHECK_10f()
+#define CHECK_008()
+#define CHECK_00f()
+#define CHECK_0f0()
+#define CHECK_1f0()
+#define CHECK_RPL()
+#define CHECK_ST(d)
+#endif
+
+ssp1601_t *ssp = NULL;
 static unsigned short *PC;
 static int g_cycles;
 
@@ -340,9 +369,6 @@ static int g_cycles;
 static int running = 0;
 static int last_iram = 0;
 #endif
-#ifdef EMBED_INTERPRETER
-static int iram_id = 0;
-#endif
 
 // -----------------------------------------------------
 // register i/o handlers
@@ -362,8 +388,7 @@ static void write_unknown(u32 d)
 // 4
 static void write_ST(u32 d)
 {
-	//if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
-	if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
+	CHECK_ST(d);
 	rST = d;
 }
 
@@ -421,7 +446,7 @@ static int get_inc(int mode)
 	return inc;
 }
 
-#define overwite_write(dst, d) \
+#define overwrite_write(dst, d) \
 { \
 	if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
 	if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
@@ -444,12 +469,9 @@ static u32 pm_io(int reg, int write, u32 d)
 		ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
 		ssp->emu_status &= ~SSP_PMC_SET;
 		if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
-			elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
+			elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1);
 #ifdef USE_DEBUGGER
 			last_iram = (ssp->RAM1[0]-1)<<1;
-#endif
-#ifdef EMBED_INTERPRETER
-			iram_id = ssp->RAM1[0];
 #endif
 		}
 		return 0;
@@ -478,7 +500,7 @@ static u32 pm_io(int reg, int write, u32 d)
 				elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
 					reg, CADDR, d, inc, (mode>>10)&1);
 				if (mode & 0x0400) {
-				       overwite_write(dram[addr], d);
+				       overwrite_write(dram[addr], d);
 				} else dram[addr] = d;
 				ssp->pmac_write[reg] += inc;
 			}
@@ -487,19 +509,13 @@ static u32 pm_io(int reg, int write, u32 d)
 				elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
 					reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
 				if (mode & 0x0400) {
-				       overwite_write(dram[addr], d);
+				       overwrite_write(dram[addr], d);
 				} else dram[addr] = d;
 				ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
 			}
 			else if ((mode & 0x47ff) == 0x001c) // IRAM
 			{
 				int inc = get_inc(mode);
-#ifdef EMBED_INTERPRETER
-				if (addr == 0x8047) {
-					iram_id &= 0xffff;
-					iram_id |= d << 16;
-				}
-#endif
 				if ((addr&0xfc00) != 0x8000)
 					elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
 				elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
@@ -554,11 +570,9 @@ static u32 read_PM0(void)
 	if (d != (u32)-1) return d;
 	elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
 	d = rPM0;
-#ifndef EMBED_INTERPRETER
 	if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
 		ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
 	}
-#endif
 	rPM0 &= ~2; // ?
 	return d;
 }
@@ -635,14 +649,12 @@ static void write_XST(u32 d)
 static u32 read_PM4(void)
 {
 	u32 d = pm_io(4, 0, 0);
-#ifndef EMBED_INTERPRETER
 	if (d == 0) {
 		switch (GET_PPC_OFFS()) {
 			case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
 			case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
 		}
 	}
-#endif
 	if (d != (u32)-1) return d;
 	// can be removed?
 	elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
@@ -694,10 +706,9 @@ static void write_PMC(u32 d)
 // 15
 static u32 read_AL(void)
 {
-	if (*(PC-1) == 0x000f) {
+	if (*(PC-1) == 0x000f)
 		elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
-		ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
-	}
+	ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
 	return rAL;
 }
 
@@ -829,30 +840,30 @@ static void ptr1_write(int op, u32 d)
 		// mod=1 (01), "+!"
 		// mod=3,      "+"
 		case 0x08:
-		case 0x18:
 		case 0x09:
-		case 0x19:
-		case 0x0a:
-		case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
+		case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
 		case 0x0b: ssp->RAM0[1] = d; return;
 		case 0x0c:
-		case 0x1c:
 		case 0x0d:
-		case 0x1d:
-		case 0x0e:
-		case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
+		case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
 		case 0x0f: ssp->RAM1[1] = d; return;
 		// mod=2 (10), "-"
 		case 0x10:
 		case 0x11:
-		case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
+		case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
 		case 0x13: ssp->RAM0[2] = d; return;
 		case 0x14:
 		case 0x15:
-		case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
+		case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
 		case 0x17: ssp->RAM1[2] = d; return;
-		// mod=3 (11)
+		// mod=3 (11), "+"
+		case 0x18:
+		case 0x19:
+		case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
 		case 0x1b: ssp->RAM0[3] = d; return;
+		case 0x1c:
+		case 0x1d:
+		case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
 		case 0x1f: ssp->RAM1[3] = d; return;
 	}
 }
@@ -890,7 +901,7 @@ static u32 ptr2_read(int op)
 
 // -----------------------------------------------------
 
-#if defined(USE_DEBUGGER) // || defined(EMBED_INTERPRETER)
+#if defined(USE_DEBUGGER)
 static void debug_dump2file(const char *fname, void *mem, int len)
 {
 	FILE *f = fopen(fname, "wb");
@@ -993,9 +1004,6 @@ static void debug(unsigned int pc, unsigned int op)
 #endif // USE_DEBUGGER
 
 
-#ifdef EMBED_INTERPRETER
-static
-#endif
 void ssp1601_reset(ssp1601_t *l_ssp)
 {
 	ssp = l_ssp;
@@ -1007,14 +1015,10 @@ void ssp1601_reset(ssp1601_t *l_ssp)
 }
 
 
-#ifdef EMBED_INTERPRETER
-static
-#endif
 void ssp1601_run(int cycles)
 {
-#ifndef EMBED_INTERPRETER
 	SET_PC(rPC);
-#endif
+
 	g_cycles = cycles;
 
 	while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
@@ -1030,9 +1034,9 @@ void ssp1601_run(int cycles)
 		{
 			// ld d, s
 			case 0x00:
+				CHECK_B_SET();
 				if (op == 0) break; // nop
 				if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
-					// not sure. MAME claims that only hi word is transfered.
 					read_P(); // update P
 					rA32 = rP.v;
 				}
@@ -1050,22 +1054,22 @@ void ssp1601_run(int cycles)
 			case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
 
 			// ldi d, imm
-			case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+			case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
 
 			// ld d, ((ri))
-			case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+			case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
 
 			// ldi (ri), imm
-			case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
+			case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
 
 			// ld adr, a
 			case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
 
 			// ld d, ri
-			case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+			case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
 
 			// ld ri, s
-			case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
+			case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
 
 			// ldi ri, simm
 			case 0x0c:
@@ -1076,27 +1080,37 @@ void ssp1601_run(int cycles)
 			// call cond, addr
 			case 0x24: {
 				int cond = 0;
+				CHECK_00f();
 				COND_CHECK
-				if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
+				if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
 				else PC++;
+				g_cycles--; // always 2 cycles
 				break;
 			}
 
 			// ld d, (a)
-			case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+			case 0x25:
+				CHECK_10f();
+				tmpv = ((unsigned short *)svp->iram_rom)[rA];
+				REG_WRITE((op & 0xf0) >> 4, tmpv);
+				g_cycles -= 2; // 3 cycles total
+				break;
 
 			// bra cond, addr
 			case 0x26: {
 				int cond = 0;
+				CHECK_00f();
 				COND_CHECK
-				if (cond) { int new_PC = *PC++; write_PC(new_PC); }
+				if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
 				else PC++;
+				g_cycles--;
 				break;
 			}
 
 			// mod cond, op
 			case 0x48: {
 				int cond = 0;
+				CHECK_008();
 				COND_CHECK
 				if (cond) {
 					switch (op & 7) {
@@ -1107,52 +1121,56 @@ void ssp1601_run(int cycles)
 						default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
 								op&7, GET_PPC_OFFS());
 					}
-					UPD_ACC_ZN // ?
+					UPD_ACC_ZN
 				}
 				break;
 			}
 
 			// mpys?
 			case 0x1b:
+				CHECK_B_CLEAR();
 				read_P(); // update P
-				rA32 -= rP.v;			// maybe only upper word?
-				UPD_ACC_ZN			// there checking flags after this
-				rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
-				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+				rA32 -= rP.v;
+				UPD_ACC_ZN
+				rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
 				break;
 
 			// mpya (rj), (ri), b
 			case 0x4b:
+				CHECK_B_CLEAR();
 				read_P(); // update P
-				rA32 += rP.v; // confirmed to be 32bit
-				UPD_ACC_ZN // ?
-				rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
-				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+				rA32 += rP.v;
+				UPD_ACC_ZN
+				rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
 				break;
 
 			// mld (rj), (ri), b
 			case 0x5b:
+				CHECK_B_CLEAR();
 				rA32 = 0;
-				rST &= 0x0fff; // ?
-				rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
-				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+				rST &= 0x0fff;
+				rST |= SSP_FLAG_Z;
+				rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+				rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
 				break;
 
 			// OP a, s
-			case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
-			case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
-			case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
-			case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
-			case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
-			case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
+			case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
+			case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
+			case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
+			case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
+			case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
+			case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
 
 			// OP a, (ri)
-			case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
-			case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
-			case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
-			case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
-			case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
-			case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
+			case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
+			case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
+			case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
+			case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
+			case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
+			case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
 
 			// OP a, adr
 			case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
@@ -1164,41 +1182,37 @@ void ssp1601_run(int cycles)
 			case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
 
 			// OP a, imm
-			case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
-			case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
-			case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
-			case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
-			case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
-			case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
+			case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
+			case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
+			case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
+			case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
+			case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
+			case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
 
 			// OP a, ((ri))
-			case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
-			case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
-			case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
-			case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
-			case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
-			case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
+			case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
+			case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
+			case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
+			case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
+			case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
+			case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
 
 			// OP a, ri
-			case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
-			case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
-			case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
-			case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
-			case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
-			case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
+			case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
+			case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
+			case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
+			case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
+			case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
+			case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
 
 			// OP simm
-			case 0x1c: OP_SUBA(op & 0xff); break;
-			case 0x3c: OP_CMPA(op & 0xff); break;
-			case 0x4c: OP_ADDA(op & 0xff); break;
-			// MAME code only does LSB of top word, but this looks wrong to me.
-			case 0x5c: OP_ANDA(op & 0xff); break;
-			case 0x6c: OP_ORA (op & 0xff); break;
-			case 0x7c: OP_EORA(op & 0xff); break;
-
-#ifdef EMBED_INTERPRETER
-			case 0x7f: goto interp_end; /* pseudo op */
-#endif
+			case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
+			case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
+			case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
+			case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
+			case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
+			case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
+
 			default:
 				elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
 				break;
@@ -1207,12 +1221,6 @@ void ssp1601_run(int cycles)
 	}
 
 	rPC = GET_PC();
-#ifdef EMBED_INTERPRETER
-interp_end:
-#endif
 	read_P(); // update P
-
-	if (ssp->gr[SSP_GR0].v != 0xffff0000)
-		elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
 }