X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=Pico%2Fcd%2FSek.c;h=8e5e45ffc3a923fecb9aa6b3fe9bc570a2eb77cd;hb=71de3cd9bb3cad7630df5b1d2a0e56475995b025;hp=00b3f16ec591d4e00e94e1a8e7b6f2a92e10e2bf;hpb=6cadc2da0070781cf2d8fcff84265d3ca1f423b9;p=picodrive.git diff --git a/Pico/cd/Sek.c b/Pico/cd/Sek.c index 00b3f16..8e5e45f 100644 --- a/Pico/cd/Sek.c +++ b/Pico/cd/Sek.c @@ -1,4 +1,4 @@ -// (c) Copyright 2006 notaz, All rights reserved. +// (c) Copyright 2007 notaz, All rights reserved. #include "../PicoInt.h" @@ -7,16 +7,22 @@ int SekCycleCntS68k=0; // cycles done in this frame int SekCycleAimS68k=0; // cycle aim + +/* context */ +// Cyclone 68000 #ifdef EMU_C68K -// ---------------------- Cyclone 68000 ---------------------- -struct Cyclone PicoCpuS68k; +struct Cyclone PicoCpuCS68k; #endif - +// MUSASHI 68000 #ifdef EMU_M68K -// ---------------------- MUSASHI 68000 ---------------------- -m68ki_cpu_core PicoS68kCPU; // Mega CD's CPU +m68ki_cpu_core PicoCpuMS68k; +#endif +// FAME 68000 +#ifdef EMU_F68K +M68K_CONTEXT PicoCpuFS68k; #endif + static int new_irq_level(int level) { int level_new = 0, irqs; @@ -28,112 +34,164 @@ static int new_irq_level(int level) return level_new; } -#ifdef EMU_M68K -static int SekIntAckS68k(int level) -{ - int level_new = new_irq_level(level); - dprintf("s68kACK %i -> %i", level, level_new); - CPU_INT_LEVEL = level_new << 8; - return M68K_INT_ACK_AUTOVECTOR; -} -#endif - #ifdef EMU_C68K -// interrupt acknowledgment -static void SekIntAckS68k(int level) +// interrupt acknowledgement +static int SekIntAckS68k(int level) { int level_new = new_irq_level(level); dprintf("s68kACK %i -> %i", level, level_new); - PicoCpuS68k.irq = level_new; + PicoCpuCS68k.irq = level_new; + return CYCLONE_INT_ACK_AUTOVECTOR; } -static void SekResetAck() +static void SekResetAckS68k(void) { dprintf("s68k: Reset encountered @ %06x", SekPcS68k); } -static int SekUnrecognizedOpcode() +static int SekUnrecognizedOpcodeS68k(void) { unsigned int pc, op; pc = SekPcS68k; - op = PicoCpuS68k.read16(pc); + op = PicoCpuCS68k.read16(pc); dprintf("Unrecognized Opcode %04x @ %06x", op, pc); //exit(1); return 0; } #endif +#ifdef EMU_M68K +static int SekIntAckMS68k(int level) +{ +#ifndef EMU_CORE_DEBUG + int level_new = new_irq_level(level); + dprintf("s68kACK %i -> %i", level, level_new); + CPU_INT_LEVEL = level_new << 8; +#else + CPU_INT_LEVEL = 0; +#endif + return M68K_INT_ACK_AUTOVECTOR; +} +#endif + +#ifdef EMU_F68K +static void SekIntAckFS68k(unsigned level) +{ + int level_new = new_irq_level(level); + dprintf("s68kACK %i -> %i", level, level_new); +#ifndef EMU_CORE_DEBUG + PicoCpuFS68k.interrupts[0] = level_new; +#else + { + extern int dbg_irq_level_sub; + dbg_irq_level_sub = level_new; + PicoCpuFS68k.interrupts[0] = 0; + } +#endif +} +#endif -int SekInitS68k() +PICO_INTERNAL int SekInitS68k() { #ifdef EMU_C68K // CycloneInit(); - memset(&PicoCpuS68k,0,sizeof(PicoCpuS68k)); - PicoCpuS68k.IrqCallback=SekIntAckS68k; - PicoCpuS68k.ResetCallback=SekResetAck; - PicoCpuS68k.UnrecognizedCallback=SekUnrecognizedOpcode; + memset(&PicoCpuCS68k,0,sizeof(PicoCpuCS68k)); + PicoCpuCS68k.IrqCallback=SekIntAckS68k; + PicoCpuCS68k.ResetCallback=SekResetAckS68k; + PicoCpuCS68k.UnrecognizedCallback=SekUnrecognizedOpcodeS68k; #endif #ifdef EMU_M68K { // Musashi is not very context friendly.. void *oldcontext = m68ki_cpu_p; - m68k_set_context(&PicoS68kCPU); + m68k_set_context(&PicoCpuMS68k); m68k_set_cpu_type(M68K_CPU_TYPE_68000); m68k_init(); - m68k_set_int_ack_callback(SekIntAckS68k); + m68k_set_int_ack_callback(SekIntAckMS68k); // m68k_pulse_reset(); // not yet, memmap is not set up m68k_set_context(oldcontext); } #endif +#ifdef EMU_F68K + { + void *oldcontext = g_m68kcontext; + g_m68kcontext = &PicoCpuFS68k; + memset(&PicoCpuFS68k, 0, sizeof(PicoCpuFS68k)); + fm68k_init(); + PicoCpuFS68k.iack_handler = SekIntAckFS68k; + PicoCpuFS68k.sr = 0x2704; // Z flag + g_m68kcontext = oldcontext; + } +#endif return 0; } // Reset the 68000: -int SekResetS68k() +PICO_INTERNAL int SekResetS68k() { if (Pico.rom==NULL) return 1; #ifdef EMU_C68K - PicoCpuS68k.stopped=0; - PicoCpuS68k.osp=0; - PicoCpuS68k.srh =0x27; // Supervisor mode - PicoCpuS68k.flags=4; // Z set - PicoCpuS68k.irq=0; - PicoCpuS68k.a[7]=PicoCpuS68k.read32(0); // Stack Pointer - PicoCpuS68k.membase=0; - PicoCpuS68k.pc=PicoCpuS68k.checkpc(PicoCpuS68k.read32(4)); // Program Counter + PicoCpuCS68k.state_flags=0; + PicoCpuCS68k.osp=0; + PicoCpuCS68k.srh =0x27; // Supervisor mode + PicoCpuCS68k.flags=4; // Z set + PicoCpuCS68k.irq=0; + PicoCpuCS68k.a[7]=PicoCpuCS68k.read32(0); // Stack Pointer + PicoCpuCS68k.membase=0; + PicoCpuCS68k.pc=PicoCpuCS68k.checkpc(PicoCpuCS68k.read32(4)); // Program Counter #endif #ifdef EMU_M68K { void *oldcontext = m68ki_cpu_p; - m68k_set_context(&PicoS68kCPU); + m68k_set_context(&PicoCpuMS68k); + m68ki_cpu.sp[0]=0; + m68k_set_irq(0); m68k_pulse_reset(); m68k_set_context(oldcontext); } #endif +#ifdef EMU_F68K + { + void *oldcontext = g_m68kcontext; + g_m68kcontext = &PicoCpuFS68k; + fm68k_reset(); + g_m68kcontext = oldcontext; + } +#endif return 0; } -int SekInterruptS68k(int irq) +PICO_INTERNAL int SekInterruptS68k(int irq) { int irqs, real_irq = 1; Pico_mcd->m.s68k_pend_ints |= 1 << irq; irqs = Pico_mcd->m.s68k_pend_ints >> 1; - while ((irqs >>= 1)) real_irq++; // this is probably only needed for Cyclone + while ((irqs >>= 1)) real_irq++; +#ifdef EMU_CORE_DEBUG + { + extern int dbg_irq_level_sub; + dbg_irq_level_sub=real_irq; + return 0; + } +#endif #ifdef EMU_C68K - PicoCpuS68k.irq=real_irq; + PicoCpuCS68k.irq=real_irq; #endif #ifdef EMU_M68K void *oldcontext = m68ki_cpu_p; - m68k_set_context(&PicoS68kCPU); - m68k_set_irq(real_irq); // raise irq (gets lowered after taken or must be done in ack) + m68k_set_context(&PicoCpuMS68k); + m68k_set_irq(real_irq); m68k_set_context(oldcontext); +#endif +#ifdef EMU_F68K + PicoCpuFS68k.interrupts[0]=real_irq; #endif return 0; }