X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2FCyclone%2FOpBranch.cpp;h=da7630696d03d0965572bad26f92d1228e9bc67e;hb=60305cdd4d832c9a0b69914a78d4668a1b4d2b48;hp=f8eb584a2398dc3b18b1ee47075a8ee504eaeeb4;hpb=3a5e6cf8477084dd63ab1eeadef88db3d218caea;p=picodrive.git

diff --git a/cpu/Cyclone/OpBranch.cpp b/cpu/Cyclone/OpBranch.cpp
index f8eb584..da76306 100644
--- a/cpu/Cyclone/OpBranch.cpp
+++ b/cpu/Cyclone/OpBranch.cpp
@@ -11,8 +11,7 @@ static void CheckPc(int reg)
   ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
   ot("  mov r4,r0\n");
 #else
-  if (reg != 4)
-    ot("  mov r4,r%i\n", reg);
+  ot("  bic r4,r%d,#1\n",reg); // we do not emulate address errors
 #endif
   ot("\n");
 }
@@ -139,8 +138,8 @@ int OpUnlk(int op)
   OpStart(op,0x10);
 
   ot(";@ Get An\n");
-  EaCalc(10, 7, 8, 2, 1);
-  EaRead(10, 0, 8, 2, 7, 1);
+  EaCalc(10, 0xf, 8, 2,   1);
+  EaRead(10,   0, 8, 2, 0xf, 1);
 
   ot("  add r11,r0,#4 ;@ A7+=4\n");
   ot("\n");
@@ -151,18 +150,19 @@ int OpUnlk(int op)
   ot("\n");
   ot(";@ An = value from stack:\n");
   EaWrite(10, 0, 8, 2, 7, 1);
-  
+
   Cycles=12;
   OpEnd(0x10);
   return 0;
 }
 
 // --------------------- Opcodes 0x4e70+ ---------------------
+// 01001110 01110ttt
 int Op4E70(int op)
 {
   int type=0;
 
-  type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr
+  type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr
 
   switch (type)
   {
@@ -181,7 +181,6 @@ int Op4E70(int op)
     SuperChange(op);
     CheckInterrupt(op);
     OpEnd(0x10);
-    SuperEnd(op);
     return 0;
 
     case 5: // rts
@@ -194,7 +193,7 @@ int Op4E70(int op)
     case 6: // trapv
     OpStart(op,0x10); Cycles=4;
     ot("  tst r9,#0x10000000\n");
-    ot("  subne r5,r5,#%i\n",30);
+    ot("  subne r5,r5,#%i\n",34);
     ot("  movne r0,#0x1c ;@ TRAPV exception\n");
     ot("  blne Exception\n");
     OpEnd(0x10);
@@ -225,7 +224,7 @@ int OpJsr(int op)
   // See if we can do this opcode:
   if (EaCanRead(sea,-1)==0) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,0);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
   OpStart(op,(op&0x40)?0:0x10);
@@ -237,7 +236,7 @@ int OpJsr(int op)
   ot(";@ Jump - Get new PC from r0\n");
   if (op&0x40)
   {
-    // Jmp - Get new PC from r0
+    // Jmp - Get new PC from r11
     ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");
     ot("\n");
   }
@@ -294,17 +293,17 @@ int OpDbra(int op)
       break;
     case 2: // hi
       ot("  tst r9,#0x60000000 ;@ hi: !C && !Z\n");
-      ot("  beq DbraTrue%.4x\n\n",op);
+      ot("  beq DbraTrue\n\n");
       break;
     case 3: // ls
       ot("  tst r9,#0x60000000 ;@ ls: C || Z\n");
-      ot("  bne DbraTrue%.4x\n\n",op);
+      ot("  bne DbraTrue\n\n");
       break;
     default:
       ot(";@ Is the condition true?\n");
       ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
       ot(";@ If so, don't dbra\n");
-      ot("  b%s DbraTrue%.4x\n\n",Cond[cc],op);
+      ot("  b%s DbraTrue\n\n",Cond[cc]);
       break;
   }
 
@@ -320,28 +319,52 @@ int OpDbra(int op)
 
     ot(";@ Check if Dn.w is -1\n");
     ot("  cmn r0,#1\n");
+
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
+    ot("  beq DbraMin1\n");
     ot("\n");
 
+    ot(";@ Get Branch offset:\n");
+    ot("  ldrsh r0,[r4]\n");
+    ot("  add r0,r4,r0 ;@ r4 = New PC\n");
+    CheckPc(0);
+#else
+    ot("\n");
     ot(";@ Get Branch offset:\n");
     ot("  ldrnesh r0,[r4]\n");
     ot("  addeq r4,r4,#2 ;@ Skip branch offset\n");
     ot("  subeq r5,r5,#4 ;@ additional cycles\n");
     ot("  addne r4,r4,r0 ;@ r4 = New PC\n");
+    ot("  bic r4,r4,#1\n"); // we do not emulate address errors
     ot("\n");
+#endif
     Cycles=12-2;
     OpEnd();
   }
   
-  if (cc==0||cc>=2)
+  //if (cc==0||cc>=2)
+  if (op==0x50c8)
   {
     ot(";@ condition true:\n");
-    ot("DbraTrue%.4x%s\n", op, ms?"":":");
+    ot("DbraTrue%s\n", ms?"":":");
     ot("  add r4,r4,#2 ;@ Skip branch offset\n");
     ot("\n");
     Cycles=12;
     OpEnd();
   }
 
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
+  if (op==0x51c8)
+  {
+    ot(";@ Dn.w is -1:\n");
+    ot("DbraMin1%s\n", ms?"":":");
+    ot("  add r4,r4,#2 ;@ Skip branch offset\n");
+    ot("\n");
+    Cycles=12+2;
+    OpEnd();
+  }
+#endif
+
   return 0;
 }
 
@@ -349,9 +372,10 @@ int OpDbra(int op)
 // Emit a Branch opcode 0110cccc nn  (cccc=condition)
 int OpBranch(int op)
 {
-  int size=0,use=0;
+  int size=0,use=0,checkpc=0;
   int offset=0;
   int cc=0;
+  char *asr_r11="";
 
   offset=(char)(op&0xff);
   cc=(op>>8)&15;
@@ -360,38 +384,54 @@ int OpBranch(int op)
   if (offset==0)  size=1;
   if (offset==-1) size=2;
 
+  if (size==2) size=0; // 000 model does not support long displacement
   if (size) use=op; // 16-bit or 32-bit
   else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
 
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
   OpStart(op,size?0x10:0);
-
-  ot(";@ Get Branch offset:\n");
-  if (size) 
-  {
-    EaCalc(0,0,0x3c,size);
-    EaRead(0,0,0x3c,size,0);
-  }
-  else
-    ot("  mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
-
-  // above code messes cycles
   Cycles=10; // Assume branch taken
 
   if (cc==1) ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");
 
-  if (cc>=2)
+  switch (cc)
   {
-    ot(";@ Is the condition true?\n");
-    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
-    ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
-    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000\n");
-
-    ot("  b%s DontBranch%.4x\n",Cond[cc^1],op);
-    ot("\n");
+    case 0: // T
+    case 1: // F
+      break;
+    case 2: // hi
+      ot("  tst r9,#0x60000000 ;@ hi: !C && !Z\n");
+      ot("  bne BccDontBranch%i\n\n",8<<size);
+      break;
+    case 3: // ls
+      ot("  tst r9,#0x60000000 ;@ ls: C || Z\n");
+      ot("  beq BccDontBranch%i\n\n",8<<size);
+      break;
+    default:
+      ot(";@ Is the condition true?\n");
+      ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
+      ot("  b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);
+      break;
   }
 
-  if (size==0) ot("  mov r0,r0,asr #24 ;@ ...shift down\n\n");
+  if (size) 
+  {
+    if (size<2)
+    {
+      ot("  ldrsh r11,[r4] ;@ Fetch Branch offset\n");
+    }
+    else
+    {
+      ot("  ldrh r2,[r4] ;@ Fetch Branch offset\n");
+      ot("  ldrh r11,[r4,#2]\n");
+      ot("  orr r11,r11,r2,lsl #16\n");
+    }
+  }
+  else
+  {
+    ot("  mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
+    asr_r11=",asr #24";
+  }
 
   ot(";@ Branch taken - Add on r0 to PC\n");
 
@@ -399,48 +439,49 @@ int OpBranch(int op)
   {
     ot(";@ Bsr - remember old PC\n");
     ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");
+    if (size) ot("  add r1,r1,#%d\n",1<<size);
     ot("  mov r1,r1, lsl #8\n");
+    ot("  ldr r2,[r7,#0x3c]\n");
     ot("  mov r1,r1, asr #8\n");
     ot("\n");
-    if (size) ot("  sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);
-    ot("  ldr r2,[r7,#0x3c]\n");
-    ot("  add r4,r4,r0 ;@ r4 = New PC\n");
     ot(";@ Push r1 onto stack\n");
     ot("  sub r0,r2,#4 ;@ Predecrement A7\n");
     ot("  str r0,[r7,#0x3c] ;@ Save A7\n");
     MemHandler(1,2);
     ot("\n");
     Cycles=18; // always 18
-    if (offset==0 || offset==-1)
-    {
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");
-      CheckPc(4);
-    }
+  }
+
+  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
+
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
+  if (offset!=0 && offset!=-1) checkpc=1;
+#endif
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16
+  if (offset==0)  checkpc=1;
+#endif
+#if USE_CHECKPC_CALLBACK
+  if (offset==-1) checkpc=1;
+#endif
+  if (checkpc)
+  {
+    CheckPc(0);
   }
   else
   {
-    if (size) ot("  sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);
-    if (offset==0 || offset==-1)
-    {
-      ot("  add r0,r4,r0 ;@ r4 = New PC\n");
-      ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");
-      CheckPc(0);
-    }
-    else
-    {
-      ot("  add r4,r4,r0 ;@ r4 = New PC\n");
-      ot("\n");
-    }
+    ot("  bic r4,r0,#1\n"); // we do not emulate address errors
+    ot("\n");
   }
 
-
   OpEnd(size?0x10:0);
 
-  if (cc>=2)
+  // since all "DontBranch" code is same for every size, output only once
+  if (cc>=2&&(op&0xff00)==0x6200)
   {
-    ot("DontBranch%.4x%s\n", op, ms?"":":");
-    Cycles+=(size==1)?  2 : -2; // Branch not taken
-    OpEnd(size?0x10:0);
+    ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");
+    if (size) ot("  add r4,r4,#%d\n",1<<size);
+    Cycles+=(size==1) ? 2 : -2; // Branch not taken
+    OpEnd(0);
   }
 
   return 0;