X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2FCyclone%2FOpLogic.cpp;h=d6b893337e0b07a8252a3a7e7411db6aded306c6;hb=fcdefcf62cb71969b456a6f27688adbeb5890bb9;hp=4a795e40a685402bb062b0046821704e7a539ec8;hpb=cc68a136aa179a5f32fe40208371eb9c2b0aadae;p=picodrive.git

diff --git a/cpu/Cyclone/OpLogic.cpp b/cpu/Cyclone/OpLogic.cpp
index 4a795e4..d6b8933 100644
--- a/cpu/Cyclone/OpLogic.cpp
+++ b/cpu/Cyclone/OpLogic.cpp
@@ -23,11 +23,11 @@ int OpBtstReg(int op)
     if (EaCanWrite(tea)==0) return 1;
   }
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   use&=~0x0e00; // Use same handler for all registers
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op);
+  OpStart(op,tea);
 
   if(type==1||type==3) {
     Cycles=8;
@@ -36,30 +36,30 @@ int OpBtstReg(int op)
     if(size>=2) Cycles+=2;
   }
 
-  EaCalc (0,0x0e00,sea,0);
-  EaRead (0,     0,sea,0,0x0e00);
+  EaCalcReadNoSE(-1,11,sea,0,0x0e00);
+
+  EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
+
   if (tea>=0x10)
-       ot("  and r10,r0,#7  ;@ mem - do mod 8\n");
-  else ot("  and r10,r0,#31 ;@ reg - do mod 32\n");
+       ot("  and r11,r11,#7  ;@ mem - do mod 8\n");  // size always 0
+  else ot("  and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2
   ot("\n");
 
-  EaCalc(11,0x003f,tea,size);
-  EaRead(11,     0,tea,size,0x003f);
   ot("  mov r1,#1\n");
-  ot("  tst r0,r1,lsl r10 ;@ Do arithmetic\n");
-  ot("  bicne r9,r9,#0x40000000\n");
-  ot("  orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
+  ot("  tst r0,r1,lsl r11 ;@ Do arithmetic\n");
+  ot("  bicne r10,r10,#0x40000000\n");
+  ot("  orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
   ot("\n");
 
   if (type>0)
   {
-    if (type==1) ot("  eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");
-    if (type==2) ot("  bic r1,r0,r1,lsl r10 ;@ Clear bit\n");
-    if (type==3) ot("  orr r1,r0,r1,lsl r10 ;@ Set bit\n");
+    if (type==1) ot("  eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");
+    if (type==2) ot("  bic r1,r0,r1,lsl r11 ;@ Clear bit\n");
+    if (type==3) ot("  orr r1,r0,r1,lsl r11 ;@ Set bit\n");
     ot("\n");
-    EaWrite(11,   1,tea,size,0x003f);
+    EaWrite(8,1,tea,size,0x003f,0,0);
   }
-  OpEnd();
+  OpEnd(tea);
 
   return 0;
 }
@@ -85,20 +85,19 @@ int OpBtstImm(int op)
     if (EaCanWrite(tea)==0) return 1;
   }
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op);
+  OpStart(op,sea,tea);
 
-  ot("  mov r10,#1\n");
   ot("\n");
-  EaCalc ( 0,0x0000,sea,0);
-  EaRead ( 0,     0,sea,0,0);
-  ot("  bic r9,r9,#0x40000000 ;@ Blank Z flag\n");
+  EaCalcReadNoSE(-1,0,sea,0,0);
+  ot("  mov r11,#1\n");
+  ot("  bic r10,r10,#0x40000000 ;@ Blank Z flag\n");
   if (tea>=0x10)
-       ot("  and r0,r0,#7 ;@ mem - do mod 8\n");
-  else ot("  and r0,r0,#0x1F ;@ reg - do mod 32\n");
-  ot("  mov r10,r10,lsl r0 ;@ Make bit mask\n");
+       ot("  and r0,r0,#7    ;@ mem - do mod 8\n");  // size always 0
+  else ot("  and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2
+  ot("  mov r11,r11,lsl r0 ;@ Make bit mask\n");
   ot("\n");
 
   if(type==1||type==3) {
@@ -108,22 +107,26 @@ int OpBtstImm(int op)
     if(size>=2) Cycles+=2;
   }
 
-  EaCalc (11,0x003f,tea,size);
-  EaRead (11,     0,tea,size,0x003f);
-  ot("  tst r0,r10 ;@ Do arithmetic\n");
-  ot("  orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
+  EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
+  ot("  tst r0,r11 ;@ Do arithmetic\n");
+  ot("  orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
   ot("\n");
 
   if (type>0)
   {
-    if (type==1) ot("  eor r1,r0,r10 ;@ Toggle bit\n");
-    if (type==2) ot("  bic r1,r0,r10 ;@ Clear bit\n");
-    if (type==3) ot("  orr r1,r0,r10 ;@ Set bit\n");
+    if (type==1) ot("  eor r1,r0,r11 ;@ Toggle bit\n");
+    if (type==2) ot("  bic r1,r0,r11 ;@ Clear bit\n");
+    if (type==3) ot("  orr r1,r0,r11 ;@ Set bit\n");
     ot("\n");
-    EaWrite(11,   1,tea,size,0x003f);
+    EaWrite(8,   1,tea,size,0x003f,0,0);
+#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
+    // this is a bit hacky (device handlers might modify cycles)
+    if (tea==0x38||tea==0x39)
+      ot("  ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
+#endif
   }
 
-  OpEnd();
+  OpEnd(sea,tea);
 
   return 0;
 }
@@ -142,38 +145,30 @@ int OpNeg(int op)
   if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;
   if (EaCanWrite(ea     )==0) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op);   Cycles=size<2?4:6;
-  if(ea >= 0x10) {
-    Cycles*=2;
-#ifdef CYCLONE_FOR_GENESIS
-    // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
-    // May be this is similar case as with TAS opcode, but this time the dummy
-    // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
-    if(type==1&&size<2) Cycles-=2;
-#endif
-  }
+  OpStart(op,ea); Cycles=size<2?4:6;
+  if(ea >= 0x10)  Cycles*=2;
 
-  EaCalc (10,0x003f,ea,size);
+  EaCalc (11,0x003f,ea,size,0,0);
 
-  if (type!=1) EaRead (10,0,ea,size,0x003f); // Don't need to read for 'clr'
+  if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)
   if (type==1) ot("\n");
 
   if (type==0)
   {
     ot(";@ Negx:\n");
     GetXBit(1);
-    if(size!=2) ot("  mov r0,r0,lsl #%i\n",size?16:24);
+    if(size!=2) ot("  mov r0,r0,asl #%i\n",size?16:24);
     ot("  rscs r1,r0,#0 ;@ do arithmetic\n");
-    ot("  orr r3,r9,#0xb0000000 ;@ for old Z\n");
+    ot("  orr r3,r10,#0xb0000000 ;@ for old Z\n");
     OpGetFlags(1,1,0);
     if(size!=2) {
-	  ot("  movs r1,r1,asr #%i\n",size?16:24);
-      ot("  orreq r9,r9,#0x40000000 ;@ possily missed Z\n");
-	}
-	ot("  andeq r9,r9,r3 ;@ fix Z\n");
+      ot("  movs r1,r1,asr #%i\n",size?16:24);
+      ot("  orreq r10,r10,#0x40000000 ;@ possily missed Z\n");
+    }
+    ot("  andeq r10,r10,r3 ;@ fix Z\n");
     ot("\n");
   }
 
@@ -181,14 +176,14 @@ int OpNeg(int op)
   {
     ot(";@ Clear:\n");
     ot("  mov r1,#0\n");
-    ot("  mov r9,#0x40000000 ;@ NZCV=0100\n");
+    ot("  mov r10,#0x40000000 ;@ NZCV=0100\n");
     ot("\n");
   }
 
   if (type==2)
   {
     ot(";@ Neg:\n");
-    if(size!=2) ot("  mov r0,r0,lsl #%i\n",size?16:24);
+    if(size!=2) ot("  mov r0,r0,asl #%i\n",size?16:24);
     ot("  rsbs r1,r0,#0\n");
     OpGetFlags(1,1);
     if(size!=2) ot("  mov r1,r1,asr #%i\n",size?16:24);
@@ -198,15 +193,21 @@ int OpNeg(int op)
   if (type==3)
   {
     ot(";@ Not:\n");
-    ot("  mvn r1,r0\n");
+    if(size!=2) {
+      ot("  mov r0,r0,asl #%i\n",size?16:24);
+      ot("  mvn r1,r0,asr #%i\n",size?16:24);
+    }
+    else
+      ot("  mvn r1,r0\n");
     ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
     OpGetFlags(0,0);
     ot("\n");
   }
 
-  EaWrite(10,     1,ea,size,0x003f);
+  if (type==1) eawrite_check_addrerr=1;
+  EaWrite(11,     1,ea,size,0x003f,0,0);
 
-  OpEnd();
+  OpEnd(ea);
 
   return 0;
 }
@@ -224,14 +225,14 @@ int OpSwap(int op)
 
   OpStart(op); Cycles=4;
 
-  EaCalc (10,0x0007,ea,2,1);
-  EaRead (10,     0,ea,2,0x0007,1);
+  EaCalc (11,0x0007,ea,2,1);
+  EaRead (11,     0,ea,2,0x0007,1);
 
   ot("  mov r1,r0,ror #16\n");
   ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
   OpGetFlags(0,0);
 
-  EaWrite(10,     1,8,2,0x0007,1);
+  EaWrite(11,     1,8,2,0x0007,1);
 
   OpEnd();
 
@@ -251,19 +252,19 @@ int OpTst(int op)
   // See if we can do this opcode:
   if (EaCanWrite(sea)==0||EaAn(sea)) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=4;
+  OpStart(op,sea); Cycles=4;
 
   EaCalc ( 0,0x003f,sea,size,1);
   EaRead ( 0,     0,sea,size,0x003f,1);
 
   ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
-  ot("  mrs r9,cpsr ;@ r9=flags\n");
+  ot("  mrs r10,cpsr ;@ r10=flags\n");
   ot("\n");
 
-  OpEnd();
+  OpEnd(sea);
   return 0;
 }
 
@@ -279,21 +280,21 @@ int OpExt(int op)
   size=(op>>6)&1;
   shift=32-(8<<size);
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
   OpStart(op); Cycles=4;
 
-  EaCalc (10,0x0007,ea,size+1);
-  EaRead (10,     0,ea,size+1,0x0007);
+  EaCalc (11,0x0007,ea,size+1,0,0);
+  EaRead (11,     0,ea,size+1,0x0007,0,0);
 
   ot("  mov r0,r0,asl #%d\n",shift);
   ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
-  ot("  mrs r9,cpsr ;@ r9=flags\n");
+  ot("  mrs r10,cpsr ;@ r10=flags\n");
   ot("  mov r1,r0,asr #%d\n",shift);
   ot("\n");
 
-  EaWrite(10,     1,ea,size+1,0x0007);
+  EaWrite(11,     1,ea,size+1,0x0007,0,0);
 
   OpEnd();
   return 0;
@@ -304,8 +305,8 @@ int OpExt(int op)
 int OpSet(int op)
 {
   int cc=0,ea=0;
-  int size=0,use=0;
-  char *cond[16]=
+  int size=0,use=0,changed_cycles=0;
+  static const char * const cond[16]=
   {
     "al","", "hi","ls","cc","cs","ne","eq",
     "vc","vs","pl","mi","ge","lt","gt","le"
@@ -319,30 +320,50 @@ int OpSet(int op)
   // See if we can do this opcode:
   if (EaCanWrite(ea)==0) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=8;
+  changed_cycles=ea<8 && cc>=2;
+  OpStart(op,ea,0,changed_cycles); Cycles=8;
   if (ea<8) Cycles=4;
 
-  ot("  mov r1,#0\n");
+  if (cc)
+    ot("  mov r1,#0\n");
 
-  if (cc!=1)
+  switch (cc)
   {
-    ot(";@ Is the condition true?\n");
-    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
-    ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
-    if ((cc&~1)==2) ot("  eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
-    ot("  mvn%s r1,r1\n",cond[cc]);
+    case 0: // T
+      ot("  mvn r1,#0\n");
+      if (ea<8) Cycles+=2;
+      break;
+    case 1: // F
+      break;
+    case 2: // hi
+      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");
+      ot("  mvneq r1,r1\n");
+      if (ea<8) ot("  subeq r5,r5,#2 ;@ Extra cycles\n");
+      break;
+    case 3: // ls
+      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");
+      ot("  mvnne r1,r1\n");
+      if (ea<8) ot("  subne r5,r5,#2 ;@ Extra cycles\n");
+      break;
+    default:
+      ot(";@ Is the condition true?\n");
+      ot("  msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");
+      ot("  mvn%s r1,r1\n",cond[cc]);
+      if (ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
+      break;
   }
 
-  if (cc!=1 && ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
   ot("\n");
 
-  EaCalc (0,0x003f, ea,size);
-  EaWrite(0,     1, ea,size,0x003f);
+  eawrite_check_addrerr=1;
+  EaCalc (0,0x003f, ea,size,0,0);
+  EaWrite(0,     1, ea,size,0x003f,0,0);
 
-  OpEnd();
+  opend_op_changes_cycles=changed_cycles;
+  OpEnd(ea,0);
   return 0;
 }
 
@@ -357,7 +378,7 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
   if (usereg)
   {
     ot(";@ Use Dn for count:\n");
-    ot("  and r2,r8,#7<<9\n");
+    ot("  and r2,r8,#0x0e00\n");
     ot("  ldr r2,[r7,r2,lsr #7]\n");
     ot("  and r2,r2,#63\n");
     ot("\n");
@@ -383,29 +404,30 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       ot("\n");
     }
 
-    if (type==0 && dir) ot("  mov r3,r0 ;@ save old value for V flag calculation\n");
+    if (type==0 && dir) ot("  adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");
 
     ot(";@ Shift register:\n");
     if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
     if (type==1) ot("  movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);
 
-    if (dir==0 && size<2)
-    {
-      ot(";@ restore after right shift:\n");
-      ot("  mov r0,r0,lsl #%d\n",32-(8<<size));
-      ot("\n");
-    }
-
     OpGetFlags(0,0);
     if (usereg) { // store X only if count is not 0
       ot("  cmp %s,#0 ;@ shifting by 0?\n",pct);
-      ot("  biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");
-      ot("  movne r1,r9,lsr #28\n");
-      ot("  strneb r1,[r7,#0x45] ;@ else Save X bit\n");
+      ot("  biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");
+      ot("  strne r10,[r7,#0x4c] ;@ else Save X bit\n");
     } else {
       // count will never be 0 if we use immediate
-      ot("  mov r1,r9,lsr #28\n");
-      ot("  strb r1,[r7,#0x45] ;@ Save X bit\n");
+      ot("  str r10,[r7,#0x4c] ;@ Save X bit\n");
+    }
+    ot("\n");
+
+    if (dir==0 && size<2)
+    {
+      ot(";@ restore after right shift:\n");
+      ot("  movs r0,r0,lsl #%d\n",32-(8<<size));
+      if (type)
+        ot("  orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");
+      ot("\n");
     }
 
     if (type==0 && dir) {
@@ -413,11 +435,11 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       ot("  mov r1,#0x80000000\n");
       ot("  ands r3,r3,r1,asr %s\n", pct);
       ot("  cmpne r3,r1,asr %s\n", pct);
-      ot("  biceq r9,r9,#0x10000000\n");
-      ot("  orrne r9,r9,#0x10000000\n");
+      ot("  eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this
+      ot("  tsteq r1,#0x80000000\n");
+      ot("  orrne r10,r10,#0x10000000\n");
+      ot("\n");
     }
-
-    ot("\n");
   }
 
   // --------------------------------------
@@ -426,35 +448,44 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     int wide=8<<size;
 
     // Roxr
-    if(count == 1) {
+    if(count == 1)
+    {
       if(dir==0) {
         if(size!=2) {
-		  ot("  orr r0,r0,r0,lsr #%i\n", size?16:24);
-		  ot("  bic r0,r0,#0x%x\n", 1<<(32-wide));
-		}
+          ot("  orr r0,r0,r0,lsr #%i\n", size?16:24);
+          ot("  bic r0,r0,#0x%x\n", 1<<(32-wide));
+        }
         GetXBit(0);
         ot("  movs r0,r0,rrx\n");
         OpGetFlags(0,1);
       } else {
-        ot("  ldrb r3,[r7,#0x45]\n");
+        ot("  ldr r3,[r7,#0x4c]\n");
         ot("  movs r0,r0,lsl #1\n");
         OpGetFlags(0,1);
-        ot("  tst r3,#2\n");
+        ot("  tst r3,#0x20000000\n");
         ot("  orrne r0,r0,#0x%x\n", 1<<(32-wide));
-        ot("  bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");
+        ot("  bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");
       }
-      ot("  bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
+      ot("  bic r10,r10,#0x10000000 ;@ make suve V is clear\n");
       return 0;
     }
 
     if (usereg)
     {
-      ot(";@ Reduce r2 until <0:\n");
-      ot("Reduce_%.4x%s\n",op,ms?"":":");
-      ot("  subs r2,r2,#%d\n",wide+1);
-      ot("  bpl Reduce_%.4x\n",op);
-      ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
-      ot("  beq norotx%.4x\n",op);
+      if (size==2)
+      {
+        ot("  subs r2,r2,#33\n");
+        ot("  addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);
+      }
+      else
+      {
+        ot(";@ Reduce r2 until <0:\n");
+        ot("Reduce_%.4x%s\n",op,ms?"":":");
+        ot("  subs r2,r2,#%d\n",wide+1);
+        ot("  bpl Reduce_%.4x\n",op);
+        ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
+      }
+      ot("  beq norotx_%.4x\n",op);
       ot("\n");
     }
 
@@ -470,36 +501,31 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
 
     if (shift) ot("  mov r0,r0,lsr #%d ;@ Shift down\n",shift);
 
+    ot("\n");
+    ot(";@ First get X bit (middle):\n");
+    ot("  ldr r3,[r7,#0x4c]\n");
+    ot("  rsb r1,r2,#%d\n",wide);
+    ot("  and r3,r3,#0x20000000\n");
+    ot("  mov r3,r3,lsr #29\n");
+    ot("  mov r3,r3,lsl r1\n");
+
     ot(";@ Rotate bits:\n");
-    ot("  mov r3,r0,lsr r2 ;@ Get right part\n");
+    ot("  orr r3,r3,r0,lsr r2 ;@ Orr right part\n");
     ot("  rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
-    ot("  movs r0,r0,lsl r2 ;@ Get left part\n");
-    ot("  orr r0,r3,r0 ;@ r0=Rotated value\n");
-
-    ot(";@ Insert X bit into r2-1:\n");
-    ot("  ldrb r3,[r7,#0x45]\n");
-    ot("  sub r2,r2,#1\n");
-    ot("  and r3,r3,#2\n");
-    ot("  mov r3,r3,lsr #1\n");
-    ot("  orr r0,r0,r3,lsl r2\n");
+    ot("  orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");
     ot("\n");
 
     if (shift) ot("  movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
     OpGetFlags(0,!usereg);
-    if (!shift) {
-      ot("  tst r0,r0\n");
-      ot("  bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");
-    }
     if (usereg) { // store X only if count is not 0
-      ot("  mov r2,r9,lsr #28\n");
-      ot("  strb r2,[r7,#0x45] ;@ if not 0, Save X bit\n");
+      ot("  str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");
       ot("  b nozerox%.4x\n",op);
-      ot("norotx%.4x%s\n",op,ms?"":":");
-      ot("  ldrb r2,[r7,#0x45]\n");
+      ot("norotx_%.4x%s\n",op,ms?"":":");
+      ot("  ldr r2,[r7,#0x4c]\n");
       ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
       OpGetFlags(0,0);
-      ot("  and r2,r2,#2\n");
-      ot("  orr r9,r9,r2,lsl #28 ;@ C = old_X\n");
+      ot("  and r2,r2,#0x20000000\n");
+      ot("  orr r10,r10,r2 ;@ C = old_X\n");
       ot("nozerox%.4x%s\n",op,ms?"":":");
     }
 
@@ -519,9 +545,10 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     }
 
     ot(";@ Rotate register:\n");
+    if (!dir) ot("  adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0
     if (count<0)
     {
-      if (dir) ot("  rsbs %s,%s,#32\n",pct,pct);
+      if (dir) ot("  rsb %s,%s,#32\n",pct,pct);
       ot("  movs r0,r0,ror %s\n",pct);
     }
     else
@@ -532,9 +559,9 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
     }
 
     OpGetFlags(0,0);
-    if (!dir) ot("  bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
     if (dir)
     {
+      ot("  bic r10,r10,#0x30000000 ;@ clear CV\n");
       ot(";@ Get carry bit from bit 0:\n");
       if (usereg)
       {
@@ -543,15 +570,7 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       }
       else
         ot("  tst r0,#1\n");
-      ot("  orrne r9,r9,#0x20000000\n");
-      ot("  biceq r9,r9,#0x20000000\n");
-    }
-    else if (usereg)
-    {
-      // if we rotate something by 0, ARM doesn't clear C
-      // so we need to detect that
-      ot("  cmp %s,#0\n",pct);
-      ot("  biceq r9,r9,#0x20000000\n");
+      ot("  orrne r10,r10,#0x20000000\n");
     }
     ot("\n");
 
@@ -569,7 +588,6 @@ int OpAsr(int op)
   int count=0,dir=0;
   int size=0,usereg=0,type=0;
 
-  ea=0;
   count =(op>>9)&7;
   dir   =(op>>8)&1;
   size  =(op>>6)&3;
@@ -582,22 +600,23 @@ int OpAsr(int op)
   // Use the same opcode for target registers:
   use=op&~0x0007;
 
-  // As long as count is not 8, use the same opcode for all shift counts::
+  // As long as count is not 8, use the same opcode for all shift counts:
   if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
   if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn
 
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=size<2?6:8;
+  OpStart(op,ea,0,count<0); Cycles=size<2?6:8;
 
-  EaCalc(10,0x0007, ea,size,1);
-  EaRead(10,     0, ea,size,0x0007,1);
+  EaCalc(11,0x0007, ea,size,1);
+  EaRead(11,     0, ea,size,0x0007,1);
 
   EmitAsr(op,type,dir,count, size,usereg);
 
-  EaWrite(10,    0, ea,size,0x0007,1);
+  EaWrite(11,    0, ea,size,0x0007,1);
 
-  OpEnd();
+  opend_op_changes_cycles = (count<0);
+  OpEnd(ea,0);
 
   return 0;
 }
@@ -616,23 +635,23 @@ int OpAsrEa(int op)
   if (EaCanRead(ea,0)==0) return 1;
   if (EaCanWrite(ea)==0) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=6; // EmitAsr() will add 2
+  OpStart(op,ea); Cycles=6; // EmitAsr() will add 2
 
-  EaCalc (10,0x003f,ea,size,1);
-  EaRead (10,     0,ea,size,0x003f,1);
+  EaCalc (11,0x003f,ea,size,1);
+  EaRead (11,     0,ea,size,0x003f,1);
 
   EmitAsr(op,type,dir,1,size,0);
 
-  EaWrite(10,     0,ea,size,0x003f,1);
+  EaWrite(11,     0,ea,size,0x003f,1);
 
-  OpEnd();
+  OpEnd(ea);
   return 0;
 }
 
-int OpTas(int op)
+int OpTas(int op, int gen_special)
 {
   int ea=0;
   int use=0;
@@ -642,14 +661,18 @@ int OpTas(int op)
   // See if we can do this opcode:
   if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;
 
-  use=OpBase(op);
+  use=OpBase(op,0);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=4;
+  if (!gen_special) OpStart(op,ea);
+  else
+    ot("Op%.4x_%s\n", op, ms?"":":");
+
+  Cycles=4;
   if(ea>=8) Cycles+=10;
 
-  EaCalc (10,0x003f,ea,0,1);
-  EaRead (10,     1,ea,0,0x003f,1);
+  EaCalc (11,0x003f,ea,0,1);
+  EaRead (11,     1,ea,0,0x003f,1);
 
   ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
   OpGetFlags(0,0);
@@ -657,16 +680,23 @@ int OpTas(int op)
 
 #if CYCLONE_FOR_GENESIS
   // the original Sega hardware ignores write-back phase (to memory only)
-  if (ea < 0x10) {
+  if (ea < 0x10 || gen_special) {
 #endif
     ot("  orr r1,r1,#0x80000000 ;@ set bit7\n");
 
-    EaWrite(10,     1,ea,0,0x003f,1);
+    EaWrite(11,     1,ea,0,0x003f,1);
 #if CYCLONE_FOR_GENESIS
   }
 #endif
 
-  OpEnd();
+  OpEnd(ea);
+
+#if (CYCLONE_FOR_GENESIS == 2)
+  if (!gen_special && ea >= 0x10) {
+    OpTas(op, 1);
+  }
+#endif
+
   return 0;
 }