X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2FCyclone%2FOpMove.cpp;h=1bc7a516a6535cea64ab60a15f1941d838c5000b;hb=e28a980fb7737edcf70fbce20c77b64fa14264a2;hp=1d7165bab1471cc1f25a5ffa1891cb2699755de7;hpb=03c5768cb5cb2cd8a7ea3e4383fd10065d27970e;p=picodrive.git

diff --git a/cpu/Cyclone/OpMove.cpp b/cpu/Cyclone/OpMove.cpp
index 1d7165b..1bc7a51 100644
--- a/cpu/Cyclone/OpMove.cpp
+++ b/cpu/Cyclone/OpMove.cpp
@@ -21,7 +21,7 @@ void OpFlagsToReg(int high)
 
 // Convert SR/CRR register in r0 to our flags
 // trashes r0,r1
-void OpRegToFlags(int high)
+void OpRegToFlags(int high, int srh_reg)
 {
   ot("  eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
   ot("  mov r2,r0,lsl #25\n");
@@ -32,44 +32,44 @@ void OpRegToFlags(int high)
 
   if (high)
   {
-    ot("  mov r0,r0,ror #8\n");
-    ot("  and r0,r0,#0xa7 ;@ only take defined bits\n");
-    ot("  strb r0,[r7,#0x44] ;@ Store SR high\n");
+    int mask=EMULATE_TRACE?0xa7:0x27;
+    ot("  mov r%i,r0,ror #8\n",srh_reg);
+    ot("  and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);
+    ot("  strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);
   }
   ot("\n");
 }
 
-// checks for supervisor bit, if not set, jumps to SuperEnd()
-// also sets r11 to SR high value, SuperChange() uses this
-void SuperCheck(int op)
-{
-  ot("  ldr r11,[r7,#0x44] ;@ Get SR high\n");
-  ot("  tst r11,#0x20 ;@ Check we are in supervisor mode\n");
-  ot("  beq WrongPrivilegeMode ;@ No\n");
-  ot("\n");
-}
-
 void SuperEnd(void)
 {
   ot(";@ ----------\n");
   ot(";@ tried execute privileged instruction in user mode\n");
   ot("WrongPrivilegeMode%s\n",ms?"":":");
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
+  ot("  ldr r1,[r7,#0x58]\n");
+  ot("  sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
+  ot("  orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
+  ot("  str r1,[r7,#0x58]\n");
+#else
   ot("  sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
-  ot("  mov r0,#0x20 ;@ privilege violation\n");
+#endif
+  ot("  mov r0,#8 ;@ privilege violation\n");
   ot("  bl Exception\n");
   Cycles=34;
-  OpEnd(0x10);
+  OpEnd(0);
 }
 
 // does OSP and A7 swapping if needed
 // new or old SR (not the one already in [r7,#0x44]) should be passed in r11
-// trashes r0,r11
-void SuperChange(int op,int load_srh)
+// uses srh from srh_reg (loads if < 0), trashes r0,r11
+void SuperChange(int op,int srh_reg)
 {
   ot(";@ A7 <-> OSP?\n");
-  if (load_srh)
+  if (srh_reg < 0) {
     ot("  ldr r0,[r7,#0x44] ;@ Get other SR high\n");
-  ot("  eor r0,r0,r11\n");
+    srh_reg=0;
+  }
+  ot("  eor r0,r%i,r11\n",srh_reg);
   ot("  tst r0,#0x20\n");
   ot("  beq no_sp_swap%.4x\n",op);
   ot(" ;@ swap OSP and A7:\n");
@@ -132,20 +132,21 @@ int OpMove(int op)
 
   if (movea) size=2; // movea always expands to 32-bits
 
+  eawrite_check_addrerr=1;
 #if SPLIT_MOVEL_PD
-  EaCalc (10,0x0e00,tea,size,0,0);
   if ((tea&0x38)==0x20 && size==2) { // -(An)
+    EaCalc (10,0x0e00,tea,size,0,0);
     ot("  mov r11,r1\n");
     ot("  add r0,r10,#2\n");
     EaWrite(0,     1,tea,1,0x0e00,0,0);
     EaWrite(10,   11,tea,1,0x0e00,1);
-  } else {
-    EaWrite(0,     1,tea,size,0x0e00,0,0);
   }
-#else
-  EaCalc (0,0x0e00,tea,size,0,0);
-  EaWrite(0,     1,tea,size,0x0e00,0,0);
+  else
 #endif
+  {
+    EaCalc (0,0x0e00,tea,size,0,0);
+    EaWrite(0,     1,tea,size,0x0e00,0,0);
+  }
 
 #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
   // this is a bit hacky
@@ -177,6 +178,7 @@ int OpLea(int op)
 
   OpStart(op,sea,tea);
 
+  eawrite_check_addrerr=1;
   EaCalc (1,0x003f,sea,0); // Lea
   EaCalc (0,0x0e00,tea,2);
   EaWrite(0,     1,tea,2,0x0e00);
@@ -217,14 +219,14 @@ int OpMoveSr(int op)
   use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op,ea);
+  // 68000 model allows reading whole SR in user mode (but newer models don't)
+  OpStart(op,ea,0,0,type==3);
   Cycles=12;
   if (type==0) Cycles=(ea>=8)?8:6;
 
-  if (type==3) SuperCheck(op); // 68000 model allows reading whole SR in user mode (but newer models don't)
-
   if (type==0 || type==1)
   {
+    eawrite_check_addrerr=1;
     OpFlagsToReg(type==0);
     EaCalc (0,0x003f,ea,size,0,0);
     EaWrite(0,     1,ea,size,0x003f,0,0);
@@ -233,10 +235,13 @@ int OpMoveSr(int op)
   if (type==2 || type==3)
   {
     EaCalcReadNoSE(-1,0,ea,size,0x003f);
-    OpRegToFlags(type==3);
+    OpRegToFlags(type==3,1);
     if (type==3) {
-      SuperChange(op,0);
-      CheckInterrupt(op);
+      SuperChange(op,1);
+      opend_check_interrupt = 1;
+      opend_check_trace = 1;
+      OpEnd(ea);
+      return 0;
     }
   }
 
@@ -251,6 +256,7 @@ int OpArithSr(int op)
 {
   int type=0,ea=0;
   int use=0,size=0;
+  int sr_mask=EMULATE_TRACE?0xa7:0x27;
 
   type=(op>>9)&5; if (type==4) return 1;
   size=(op>>6)&1; // ccr or sr?
@@ -259,22 +265,53 @@ int OpArithSr(int op)
   use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op,ea); Cycles=16;
+  OpStart(op,ea,0,0,size!=0); Cycles=16;
+
+  EaCalcRead(-1,0,ea,size,0x003f);
 
-  if (size) SuperCheck(op);
+  ot("  eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
+  ot("  tst r1,#1           ;@ 1 if C!=V\n");
+  ot("  eorne r0,r0,#3      ;@ ___XNZCV\n");
+  ot("  ldr r2,[r7,#0x4c]   ;@ Load old X bit\n");
+
+  // note: old srh is already in r11 (done by OpStart)
+  if (type==0) {
+    ot("  orr r9,r9,r0,lsl #28\n");
+    ot("  orr r2,r2,r0,lsl #25 ;@ X bit\n");
+    if (size!=0) {
+      ot("  orr r1,r11,r0,lsr #8\n");
+      ot("  and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
+    }
+  }
+  if (type==1) {
+    ot("  and r9,r9,r0,lsl #28\n");
+    ot("  and r2,r2,r0,lsl #25 ;@ X bit\n");
+    if (size!=0)
+      ot("  and r1,r11,r0,lsr #8\n");
+  }
+  if (type==5) {
+    ot("  eor r9,r9,r0,lsl #28\n");
+    ot("  eor r2,r2,r0,lsl #25 ;@ X bit\n");
+    if (size!=0) {
+      ot("  eor r1,r11,r0,lsr #8\n");
+      ot("  and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
+    }
+  }
 
-  EaCalc(10,0x003f,ea,size);
-  EaRead(10,    10,ea,size,0x003f);
+  ot("  str r2,[r7,#0x4c]   ;@ Save X bit\n");
+  if (size!=0)
+    ot("  strb r1,[r7,#0x44]\n");
+  ot("\n");
 
-  OpFlagsToReg(size);
-  if (type==0) ot("  orr r0,r1,r10\n");
-  if (type==1) ot("  and r0,r1,r10\n");
-  if (type==5) ot("  eor r0,r1,r10\n");
-  OpRegToFlags(size);
-  if (size) {
-    SuperChange(op,0);
-    CheckInterrupt(op);
+  // we can't enter supervisor mode, nor unmask irqs just by using OR
+  if (size!=0 && type!=0) {
+    SuperChange(op,1);
+    ot("\n");
+    opend_check_interrupt = 1;
   }
+  // also can't set trace bit with AND
+  if (size!=0 && type!=1)
+    opend_check_trace = 1;
 
   OpEnd(ea);
 
@@ -337,7 +374,7 @@ int OpMovem(int op)
   use=OpBase(op,size);
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op,ea);
+  OpStart(op,ea,0,1);
 
   ot("  ldrh r11,[r4],#2 ;@ r11=register mask\n");
 
@@ -353,6 +390,13 @@ int OpMovem(int op)
   ot("  tst r11,r11\n");        // sanity check
   ot("  beq NoRegs%.4x\n",op);
 
+#if EMULATE_ADDRESS_ERRORS_IO
+  ot("\n");
+  ot("  tst r6,#1 ;@ address error?\n");
+  ot("  movne r0,r6\n");
+  ot("  bne ExceptionAddressError_%c_data\n",dir?'r':'w');
+#endif
+
   ot("\n");
   ot("Movemloop%.4x%s\n",op, ms?"":":");
   ot("  add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);
@@ -365,6 +409,7 @@ int OpMovem(int op)
   if (dir)
   {
     ot("  ;@ Copy memory to register:\n",1<<size);
+    earead_check_addrerr=0; // already checked
     EaRead (6,0,ea,size,0x003f);
     ot("  str r0,[r7,r10] ;@ Save value into Dn/An\n");
   }
@@ -372,7 +417,19 @@ int OpMovem(int op)
   {
     ot("  ;@ Copy register to memory:\n",1<<size);
     ot("  ldr r1,[r7,r10] ;@ Load value from Dn/An\n");
-    EaWrite(6,1,ea,size,0x003f);
+#if SPLIT_MOVEL_PD
+    if (decr && size==2) { // -(An)
+      ot("  add r0,r6,#2\n");
+      EaWrite(0,1,ea,1,0x003f,0,0);
+      ot("  ldr r1,[r7,r10] ;@ Load value from Dn/An\n");
+      ot("  mov r0,r6\n");
+      EaWrite(0,1,ea,1,0x003f,1);
+    }
+    else
+#endif
+    {
+      EaWrite(6,1,ea,size,0x003f);
+    }
   }
 
   if (decr==0) ot("  add r6,r6,#%d ;@ Post-increment address\n",1<<size);
@@ -403,6 +460,7 @@ int OpMovem(int op)
 
   Cycles+=Ea_add_ns(g_movem_cycle_table,ea);
 
+  opend_op_changes_cycles = 1;
   OpEnd(ea);
   ltorg();
   ot("\n");
@@ -421,12 +479,11 @@ int OpMoveUsp(int op)
 
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
 
-  OpStart(op); Cycles=4;
-
-  SuperCheck(op);
+  OpStart(op,0,0,0,1); Cycles=4;
 
   if (dir)
   {
+    eawrite_check_addrerr=1;
     ot("  ldr r1,[r7,#0x48] ;@ Get from USP\n\n");
     EaCalc (0,0x000f,8,2,1);
     EaWrite(0,     1,8,2,0x000f,1);
@@ -572,9 +629,7 @@ int OpStopReset(int op)
 {
   int type=(op>>1)&1; // stop/reset
 
-  OpStart(op);
-
-  SuperCheck(op);
+  OpStart(op,0,0,0,1);
 
   if(type) {
     // copy immediate to SR, stop the CPU and eat all remaining cycles.
@@ -584,11 +639,12 @@ int OpStopReset(int op)
 
     ot("\n");
 
-    ot("  mov r0,#1\n");
-    ot("  str r0,[r7,#0x58] ;@ stopped\n");
+    ot("  ldr r0,[r7,#0x58]\n");
+    ot("  mov r5,#0 ;@ eat cycles\n");
+    ot("  orr r0,r0,#1 ;@ stopped\n");
+    ot("  str r0,[r7,#0x58]\n");
     ot("\n");
 
-    ot("  mov r5,#0 ;@ eat cycles\n");
     Cycles = 4;
     ot("\n");
   }