X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_arm.c;h=53c235f291ff51c59c975558f86af4d6fdd8ef7d;hb=cff531af94bd9c9c89ae162e80f48ddc26a4e504;hp=6a115e37c67bd3e007693e666c3f9f9f429624ca;hpb=e05b81fc5b3f640496795ced5d893ece4cc51c2d;p=picodrive.git

diff --git a/cpu/drc/emit_arm.c b/cpu/drc/emit_arm.c
index 6a115e3..53c235f 100644
--- a/cpu/drc/emit_arm.c
+++ b/cpu/drc/emit_arm.c
@@ -1,8 +1,10 @@
-// Basic macros to emit ARM instructions and some utils
-
-// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
-// Free for non-commercial use.
-
+/*
+ * Basic macros to emit ARM instructions and some utils
+ * Copyright (C) 2008,2009,2010 notaz
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
+ */
 #define CONTEXT_REG 11
 
 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
@@ -169,7 +171,8 @@
 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 
 /* ldr and str */
-#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
+#define EOP_LDR_IMM2(cond,rd,rn,offset_12)  EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
+#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
 
 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
@@ -179,6 +182,8 @@
 
 #define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
 
+#define EOP_LDRH_IMM2(cond,rd,rn,offset_8)  EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
+
 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
@@ -238,30 +243,45 @@
 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 
 
-// XXX: AND, RSB, *C, MVN will break if 1 insn is not enough
+// XXX: AND, RSB, *C, will break if 1 insn is not enough
 static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
 {
 	int ror2;
 	u32 v;
 
-	if (op == A_OP_MOV) {
+	switch (op) {
+	case A_OP_MOV:
 		rn = 0;
-		if (~imm < 0x100) {
+		if (~imm < 0x10000) {
 			imm = ~imm;
 			op = A_OP_MVN;
 		}
-	} else if (imm == 0)
-		return;
+		break;
+
+	case A_OP_EOR:
+	case A_OP_SUB:
+	case A_OP_ADD:
+	case A_OP_ORR:
+	case A_OP_BIC:
+		if (s == 0 && imm == 0)
+			return;
+		break;
+	}
 
-	for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
+	for (v = imm, ror2 = 0; ; ror2 -= 8/2) {
 		/* shift down to get 'best' rot2 */
 		for (; v && !(v & 3); v >>= 2)
 			ror2--;
 
 		EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
 
+		v >>= 8;
+		if (v == 0)
+			break;
 		if (op == A_OP_MOV)
 			op = A_OP_ORR;
+		if (op == A_OP_MVN)
+			op = A_OP_BIC;
 		rn = rd;
 	}
 }
@@ -314,8 +334,8 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	tcache_ptr += sizeof(u32)
 
 #define JMP_EMIT(cond, ptr) { \
-	int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
-	EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
+	u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
+	EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
 }
 
 #define EMITH_JMP_START(cond) { \
@@ -327,11 +347,14 @@ static int emith_xbranch(int cond, void *target, int is_call)
 }
 
 // fake "simple" or "short" jump - using cond insns instead
-#define EMITH_SJMP_START(cond) \
+#define EMITH_NOTHING1(cond) \
 	(void)(cond)
 
-#define EMITH_SJMP_END(cond) \
-	(void)(cond)
+#define EMITH_SJMP_START(cond)	EMITH_NOTHING1(cond)
+#define EMITH_SJMP_END(cond)	EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_START(cond)	EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_MID(cond)	EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_END()
 
 #define emith_move_r_r(d, s) \
 	EOP_MOV_REG_SIMPLE(d, s)
@@ -408,6 +431,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_add_r_imm(r, imm) \
 	emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
 
+#define emith_adc_r_imm(r, imm) \
+	emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
+
 #define emith_sub_r_imm(r, imm) \
 	emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
 
@@ -485,8 +511,11 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_asr(d, s, cnt) \
 	EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
 
+#define emith_ror_c(cond, d, s, cnt) \
+	EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
+
 #define emith_ror(d, s, cnt) \
-	EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
+	emith_ror_c(A_COND_AL, d, s, cnt)
 
 #define emith_rol(d, s, cnt) \
 	EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
@@ -536,8 +565,26 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
 
 // misc
+#define emith_read_r_r_offs_c(cond, r, rs, offs) \
+	EOP_LDR_IMM2(cond, r, rs, offs)
+
+#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
+	EOP_LDRB_IMM2(cond, r, rs, offs)
+
+#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
+	EOP_LDRH_IMM2(cond, r, rs, offs)
+
+#define emith_read_r_r_offs(r, rs, offs) \
+	emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
+
+#define emith_read8_r_r_offs(r, rs, offs) \
+	emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
+
+#define emith_read16_r_r_offs(r, rs, offs) \
+	emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
+
 #define emith_ctx_read(r, offs) \
-	EOP_LDR_IMM(r, CONTEXT_REG, offs)
+	emith_read_r_r_offs(r, CONTEXT_REG, offs)
 
 #define emith_ctx_write(r, offs) \
 	EOP_STR_IMM(r, CONTEXT_REG, offs)
@@ -585,9 +632,6 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	EOP_MOV_REG_ASR(d,d,32 - (bits)); \
 }
 
-#define host_arg2reg(rd, arg) \
-	rd = arg
-
 // upto 4 args
 #define emith_pass_arg_r(arg, reg) \
 	EOP_MOV_REG_SIMPLE(arg, reg)
@@ -598,18 +642,26 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_jump(target) \
 	emith_jump_cond(A_COND_AL, target)
 
+#define emith_jump_patchable(target) \
+	emith_jump(target)
+
 #define emith_jump_cond(cond, target) \
 	emith_xbranch(cond, target, 0)
 
-#define emith_jump_patchable(cond) \
-	emith_jump_cond(cond, 0)
+#define emith_jump_cond_patchable(cond, target) \
+	emith_jump_cond(cond, target)
 
 #define emith_jump_patch(ptr, target) do { \
 	u32 *ptr_ = ptr; \
-	u32 val = (u32 *)(target) - (u32 *)ptr_ - 2; \
-	*ptr_ = (*ptr_ & 0xff000000) | (val & 0x00ffffff); \
+	u32 val_ = (u32 *)(target) - ptr_ - 2; \
+	*ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
 } while (0)
 
+#define emith_jump_at(ptr, target) { \
+	u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
+	EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
+}
+
 #define emith_jump_reg_c(cond, r) \
 	EOP_C_BX(cond, r)
 
@@ -642,6 +694,18 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_ret_to_ctx(offs) \
 	emith_ctx_write(14, offs)
 
+#define emith_push_ret() \
+	EOP_STMFD_SP(A_R14M)
+
+#define emith_pop_and_ret() \
+	EOP_LDMFD_SP(A_R15M)
+
+#define host_instructions_updated(base, end) \
+	cache_flush_d_inval_i(base, end)
+
+#define host_arg2reg(rd, arg) \
+	rd = arg
+
 /* SH2 drc specific */
 #define emith_sh2_drc_entry() \
 	EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M)