X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_arm.c;h=7b5566dda5056c98f595ccdd54d30c3362bf56b7;hb=898d51a7fd1c090799ac88869fa0daf096fd702f;hp=51954835813c42fb5ced6e5e64227338671eb438;hpb=8b4f38f4c6977ff80fff0ec92228914fe930e534;p=picodrive.git diff --git a/cpu/drc/emit_arm.c b/cpu/drc/emit_arm.c index 5195483..7b5566d 100644 --- a/cpu/drc/emit_arm.c +++ b/cpu/drc/emit_arm.c @@ -1,9 +1,12 @@ -// Basic macros to emit ARM instructions and some utils - -// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas -// Free for non-commercial use. - +/* + * Basic macros to emit ARM instructions and some utils + * Copyright (C) 2008,2009,2010 notaz + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. + */ #define CONTEXT_REG 11 +#define RET_REG 0 // XXX: tcache_ptr type for SVP and SH2 compilers differs.. #define EMIT_PTR(ptr, x) \ @@ -23,6 +26,7 @@ #define A_R9M (1 << 9) #define A_R10M (1 << 10) #define A_R11M (1 << 11) +#define A_R12M (1 << 12) #define A_R14M (1 << 14) #define A_R15M (1 << 15) @@ -155,6 +159,10 @@ #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \ EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12)) +#define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \ + EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \ + ((shift_imm)<<7) | ((shift_op)<<5) | (rm)) + /* addressing mode 3 */ #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \ EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \ @@ -165,12 +173,19 @@ #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm) /* ldr and str */ +#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12) +#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12) + #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12) #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12) #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0) #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12) #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0) +#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm) + +#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8) + #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8) #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0) #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm) @@ -192,8 +207,6 @@ #define EOP_C_BX(cond,rm) \ EMIT(((cond)<<28) | 0x012fff10 | (rm)) -#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm) - #define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \ EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24)) @@ -231,32 +244,65 @@ #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm) #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm) +#define EOP_MOVW(rd,imm) \ + EMIT(0xe3000000 | ((rd)<<12) | ((imm)&0xfff) | (((imm)<<4)&0xf0000)) +#define EOP_MOVT(rd,imm) \ + EMIT(0xe3400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000)) + +// XXX: AND, RSB, *C, will break if 1 insn is not enough static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm) { int ror2; u32 v; - if (op == A_OP_MOV) { + switch (op) { + case A_OP_MOV: rn = 0; - if (~imm < 0x100) { + if (~imm < 0x10000) { imm = ~imm; op = A_OP_MVN; } - } else if (imm == 0) - return; +#ifdef HAVE_ARMV7 + for (v = imm, ror2 = 0; v && !(v & 3); v >>= 2) + ror2--; + if (v >> 8) { + /* 2+ insns needed - prefer movw/movt */ + if (op == A_OP_MVN) + imm = ~imm; + EOP_MOVW(rd, imm); + if (imm & 0xffff0000) + EOP_MOVT(rd, imm); + return; + } +#endif + break; + + case A_OP_EOR: + case A_OP_SUB: + case A_OP_ADD: + case A_OP_ORR: + case A_OP_BIC: + if (s == 0 && imm == 0) + return; + break; + } - for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) { + for (v = imm, ror2 = 0; ; ror2 -= 8/2) { /* shift down to get 'best' rot2 */ for (; v && !(v & 3); v >>= 2) ror2--; EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff); - if (op == A_OP_MOV) { + v >>= 8; + if (v == 0) + break; + if (op == A_OP_MOV) op = A_OP_ORR; - rn = rd; - } + if (op == A_OP_MVN) + op = A_OP_BIC; + rn = rd; } } @@ -264,12 +310,12 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int emith_op_imm2(cond, s, op, r, r, imm) // test op -#define emith_top_imm(cond, op, r, imm) { \ +#define emith_top_imm(cond, op, r, imm) do { \ u32 ror2, v; \ for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \ ror2--; \ EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \ -} +} while (0) #define is_offset_24(val) \ ((val) >= (int)0xff000000 && (val) <= 0x00ffffff) @@ -308,8 +354,8 @@ static int emith_xbranch(int cond, void *target, int is_call) tcache_ptr += sizeof(u32) #define JMP_EMIT(cond, ptr) { \ - int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \ - EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \ + u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \ + EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \ } #define EMITH_JMP_START(cond) { \ @@ -321,18 +367,30 @@ static int emith_xbranch(int cond, void *target, int is_call) } // fake "simple" or "short" jump - using cond insns instead -#define EMITH_SJMP_START(cond) \ +#define EMITH_NOTHING1(cond) \ (void)(cond) -#define EMITH_SJMP_END(cond) \ - (void)(cond) +#define EMITH_SJMP_DECL_() +#define EMITH_SJMP_START_(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP_END_(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_END() #define emith_move_r_r(d, s) \ EOP_MOV_REG_SIMPLE(d, s) +#define emith_move_r_r_ptr(d, s) \ + emith_move_r_r(d, s) + #define emith_mvn_r_r(d, s) \ EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0) +#define emith_add_r_r_r_lsl(d, s1, s2, lslimm) \ + EOP_ADD_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm) + #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \ EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm) @@ -348,6 +406,9 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_eor_r_r_lsr(d, s, lsrimm) \ emith_eor_r_r_r_lsr(d, d, s, lsrimm) +#define emith_add_r_r_r(d, s1, s2) \ + emith_add_r_r_r_lsl(d, s1, s2, 0) + #define emith_or_r_r_r(d, s1, s2) \ emith_or_r_r_r_lsl(d, s1, s2, 0) @@ -355,7 +416,7 @@ static int emith_xbranch(int cond, void *target, int is_call) emith_eor_r_r_r_lsl(d, s1, s2, 0) #define emith_add_r_r(d, s) \ - EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0) + emith_add_r_r_r(d, d, s) #define emith_sub_r_r(d, s) \ EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0) @@ -402,6 +463,9 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_add_r_imm(r, imm) \ emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm) +#define emith_adc_r_imm(r, imm) \ + emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm) + #define emith_sub_r_imm(r, imm) \ emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm) @@ -461,6 +525,15 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_and_r_r_imm(d, s, imm) \ emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm) +#define emith_add_r_r_imm(d, s, imm) \ + emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm) + +#define emith_add_r_r_ptr_imm(d, s, imm) \ + emith_add_r_r_imm(d, s, imm) + +#define emith_sub_r_r_imm(d, s, imm) \ + emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm) + #define emith_neg_r_r(d, s) \ EOP_RSB_IMM(d, s, 0, 0) @@ -473,8 +546,11 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_asr(d, s, cnt) \ EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt) +#define emith_ror_c(cond, d, s, cnt) \ + EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt) + #define emith_ror(d, s, cnt) \ - EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt) + emith_ror_c(A_COND_AL, d, s, cnt) #define emith_rol(d, s, cnt) \ EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \ @@ -524,8 +600,29 @@ static int emith_xbranch(int cond, void *target, int is_call) EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2) // misc +#define emith_read_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDR_IMM2(cond, r, rs, offs) + +#define emith_read8_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDRB_IMM2(cond, r, rs, offs) + +#define emith_read16_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDRH_IMM2(cond, r, rs, offs) + +#define emith_read_r_r_offs(r, rs, offs) \ + emith_read_r_r_offs_c(A_COND_AL, r, rs, offs) + +#define emith_read8_r_r_offs(r, rs, offs) \ + emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs) + +#define emith_read16_r_r_offs(r, rs, offs) \ + emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs) + #define emith_ctx_read(r, offs) \ - EOP_LDR_IMM(r, CONTEXT_REG, offs) + emith_read_r_r_offs(r, CONTEXT_REG, offs) + +#define emith_ctx_read_ptr(r, offs) \ + emith_ctx_read(r, offs) #define emith_ctx_write(r, offs) \ EOP_STR_IMM(r, CONTEXT_REG, offs) @@ -573,8 +670,20 @@ static int emith_xbranch(int cond, void *target, int is_call) EOP_MOV_REG_ASR(d,d,32 - (bits)); \ } -#define host_arg2reg(rd, arg) \ - rd = arg +#define emith_do_caller_regs(mask, func) { \ + u32 _reg_mask = (mask) & 0x500f; \ + if (_reg_mask) { \ + if (__builtin_parity(_reg_mask) == 1) \ + _reg_mask |= 0x10; /* eabi align */ \ + func(_reg_mask); \ + } \ +} + +#define emith_save_caller_regs(mask) \ + emith_do_caller_regs(mask, EOP_STMFD_SP) + +#define emith_restore_caller_regs(mask) \ + emith_do_caller_regs(mask, EOP_LDMFD_SP) // upto 4 args #define emith_pass_arg_r(arg, reg) \ @@ -583,31 +692,86 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_pass_arg_imm(arg, imm) \ emith_move_r_imm(arg, imm) -#define emith_call_cond(cond, target) \ - emith_xbranch(cond, target, 1) +#define emith_jump(target) \ + emith_jump_cond(A_COND_AL, target) + +#define emith_jump_patchable(target) \ + emith_jump(target) #define emith_jump_cond(cond, target) \ emith_xbranch(cond, target, 0) +#define emith_jump_cond_patchable(cond, target) \ + emith_jump_cond(cond, target) + +#define emith_jump_patch(ptr, target) do { \ + u32 *ptr_ = ptr; \ + u32 val_ = (u32 *)(target) - ptr_ - 2; \ + *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \ +} while (0) + +#define emith_jump_at(ptr, target) { \ + u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \ + EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \ +} + +#define emith_jump_reg_c(cond, r) \ + EOP_C_BX(cond, r) + +#define emith_jump_reg(r) \ + emith_jump_reg_c(A_COND_AL, r) + +#define emith_jump_ctx_c(cond, offs) \ + EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs) + +#define emith_jump_ctx(offs) \ + emith_jump_ctx_c(A_COND_AL, offs) + +#define emith_call_cond(cond, target) \ + emith_xbranch(cond, target, 1) + #define emith_call(target) \ emith_call_cond(A_COND_AL, target) -#define emith_jump(target) \ - emith_jump_cond(A_COND_AL, target) +#define emith_call_ctx(offs) { \ + emith_move_r_r(14, 15); \ + emith_jump_ctx(offs); \ +} -#define emith_jump_reg(r) \ - EOP_BX(r) +#define emith_ret_c(cond) \ + emith_jump_reg_c(cond, 14) + +#define emith_ret() \ + emith_ret_c(A_COND_AL) + +#define emith_ret_to_ctx(offs) \ + emith_ctx_write(14, offs) + +#define emith_push_ret() \ + EOP_STMFD_SP(A_R14M) + +#define emith_pop_and_ret() \ + EOP_LDMFD_SP(A_R15M) + +#define host_instructions_updated(base, end) \ + cache_flush_d_inval_i(base, end) + +#define host_arg2reg(rd, arg) \ + rd = arg /* SH2 drc specific */ +/* pushes r12 for eabi alignment */ #define emith_sh2_drc_entry() \ - EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M) + EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R14M) #define emith_sh2_drc_exit() \ - EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R15M) + EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R15M) -#define emith_sh2_test_t() { \ - int r = rcache_get_reg(SHR_SR, RC_GR_READ); \ - EOP_TST_IMM(r, 0, 1); \ +#define emith_sh2_wcall(a, tab) { \ + emith_lsr(12, a, SH2_WRITE_SHIFT); \ + EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \ + emith_move_r_r(2, CONTEXT_REG); \ + emith_jump_reg(12); \ } #define emith_sh2_dtbf_loop() { \ @@ -631,11 +795,10 @@ static int emith_xbranch(int cond, void *target, int is_call) rcache_free_tmp(tmp_); \ } -#define emith_write_sr(srcr) { \ - int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \ - emith_lsr(srr, srr, 12); \ - emith_or_r_r_r_lsl(srr, srr, srcr, 20); \ - emith_ror(srr, srr, 20); \ +#define emith_write_sr(sr, srcr) { \ + emith_lsr(sr, sr, 10); \ + emith_or_r_r_r_lsl(sr, sr, srcr, 22); \ + emith_ror(sr, sr, 22); \ } #define emith_carry_to_t(srr, is_sub) { \