X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_arm.c;h=8b6c14d96bba0ab73d9ab153b7eb7ea41721b00a;hb=228ee974aa6ee7e0621dcea262d51ed23999000d;hp=f651dd57c4379277d90b6c3476df1998607e8338;hpb=8796b7ee88b83c54bd09c0087e023dfac5df3e08;p=picodrive.git diff --git a/cpu/drc/emit_arm.c b/cpu/drc/emit_arm.c index f651dd5..8b6c14d 100644 --- a/cpu/drc/emit_arm.c +++ b/cpu/drc/emit_arm.c @@ -1,9 +1,11 @@ -// Basic macros to emit ARM instructions and some utils - -// (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas -// Free for non-commercial use. - -#define CONTEXT_REG 7 +/* + * Basic macros to emit ARM instructions and some utils + * Copyright (C) 2008,2009,2010 notaz + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. + */ +#define CONTEXT_REG 11 // XXX: tcache_ptr type for SVP and SH2 compilers differs.. #define EMIT_PTR(ptr, x) \ @@ -23,6 +25,7 @@ #define A_R9M (1 << 9) #define A_R10M (1 << 10) #define A_R11M (1 << 11) +#define A_R12M (1 << 12) #define A_R14M (1 << 14) #define A_R15M (1 << 15) @@ -155,6 +158,10 @@ #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \ EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12)) +#define EOP_C_AM2_REG(cond,u,b,l,rn,rd,shift_imm,shift_op,rm) \ + EMIT(((cond)<<28) | 0x07000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \ + ((shift_imm)<<7) | ((shift_op)<<5) | (rm)) + /* addressing mode 3 */ #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \ EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \ @@ -165,12 +172,19 @@ #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm) /* ldr and str */ +#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12) +#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12) + #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12) #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12) #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0) #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12) #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0) +#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm) + +#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8) + #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8) #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0) #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm) @@ -182,15 +196,16 @@ #define EOP_XXM(cond,p,u,s,w,l,rn,list) \ EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list)) -#define EOP_STMFD(rb,list) EOP_XXM(A_COND_AL,1,0,0,1,0,rb,list) -#define EOP_LDMFD(rb,list) EOP_XXM(A_COND_AL,0,1,0,1,1,rb,list) +#define EOP_STMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,0,rb,list) +#define EOP_LDMIA(rb,list) EOP_XXM(A_COND_AL,0,1,0,0,1,rb,list) + +#define EOP_STMFD_SP(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list) +#define EOP_LDMFD_SP(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list) /* branches */ #define EOP_C_BX(cond,rm) \ EMIT(((cond)<<28) | 0x012fff10 | (rm)) -#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm) - #define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \ EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24)) @@ -229,31 +244,46 @@ #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm) +// XXX: AND, RSB, *C, will break if 1 insn is not enough static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm) { int ror2; u32 v; - if (op == A_OP_MOV) { + switch (op) { + case A_OP_MOV: rn = 0; - if (~imm < 0x100) { + if (~imm < 0x10000) { imm = ~imm; op = A_OP_MVN; } - } else if (imm == 0) - return; + break; + + case A_OP_EOR: + case A_OP_SUB: + case A_OP_ADD: + case A_OP_ORR: + case A_OP_BIC: + if (s == 0 && imm == 0) + return; + break; + } - for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) { + for (v = imm, ror2 = 0; ; ror2 -= 8/2) { /* shift down to get 'best' rot2 */ for (; v && !(v & 3); v >>= 2) ror2--; EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff); - if (op == A_OP_MOV) { + v >>= 8; + if (v == 0) + break; + if (op == A_OP_MOV) op = A_OP_ORR; - rn = rd; - } + if (op == A_OP_MVN) + op = A_OP_BIC; + rn = rd; } } @@ -261,12 +291,12 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int emith_op_imm2(cond, s, op, r, r, imm) // test op -#define emith_top_imm(cond, op, r, imm) { \ +#define emith_top_imm(cond, op, r, imm) do { \ u32 ror2, v; \ for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \ ror2--; \ EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \ -} +} while (0) #define is_offset_24(val) \ ((val) >= (int)0xff000000 && (val) <= 0x00ffffff) @@ -305,8 +335,8 @@ static int emith_xbranch(int cond, void *target, int is_call) tcache_ptr += sizeof(u32) #define JMP_EMIT(cond, ptr) { \ - int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \ - EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \ + u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \ + EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \ } #define EMITH_JMP_START(cond) { \ @@ -318,11 +348,14 @@ static int emith_xbranch(int cond, void *target, int is_call) } // fake "simple" or "short" jump - using cond insns instead -#define EMITH_SJMP_START(cond) \ +#define EMITH_NOTHING1(cond) \ (void)(cond) -#define EMITH_SJMP_END(cond) \ - (void)(cond) +#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond) +#define EMITH_SJMP3_END() #define emith_move_r_r(d, s) \ EOP_MOV_REG_SIMPLE(d, s) @@ -357,6 +390,9 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_sub_r_r(d, s) \ EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0) +#define emith_adc_r_r(d, s) \ + EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0) + #define emith_and_r_r(d, s) \ EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0) @@ -396,6 +432,9 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_add_r_imm(r, imm) \ emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm) +#define emith_adc_r_imm(r, imm) \ + emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm) + #define emith_sub_r_imm(r, imm) \ emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm) @@ -455,6 +494,12 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_and_r_r_imm(d, s, imm) \ emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm) +#define emith_add_r_r_imm(d, s, imm) \ + emith_op_imm2(A_COND_AL, 0, A_OP_ADD, d, s, imm) + +#define emith_sub_r_r_imm(d, s, imm) \ + emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm) + #define emith_neg_r_r(d, s) \ EOP_RSB_IMM(d, s, 0, 0) @@ -467,8 +512,11 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_asr(d, s, cnt) \ EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt) +#define emith_ror_c(cond, d, s, cnt) \ + EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt) + #define emith_ror(d, s, cnt) \ - EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt) + emith_ror_c(A_COND_AL, d, s, cnt) #define emith_rol(d, s, cnt) \ EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \ @@ -518,28 +566,47 @@ static int emith_xbranch(int cond, void *target, int is_call) EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2) // misc +#define emith_read_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDR_IMM2(cond, r, rs, offs) + +#define emith_read8_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDRB_IMM2(cond, r, rs, offs) + +#define emith_read16_r_r_offs_c(cond, r, rs, offs) \ + EOP_LDRH_IMM2(cond, r, rs, offs) + +#define emith_read_r_r_offs(r, rs, offs) \ + emith_read_r_r_offs_c(A_COND_AL, r, rs, offs) + +#define emith_read8_r_r_offs(r, rs, offs) \ + emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs) + +#define emith_read16_r_r_offs(r, rs, offs) \ + emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs) + #define emith_ctx_read(r, offs) \ - EOP_LDR_IMM(r, CONTEXT_REG, offs) - -#define emith_ctx_read_multiple(r, offs, count, tmpr) do { \ - int v_, r_ = r, c_ = count; \ - for (v_ = 0; c_; c_--, r_++) \ - v_ |= 1 << r_; \ - EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2); \ - EOP_LDMFD(tmpr,v_); \ -} while(0) + emith_read_r_r_offs(r, CONTEXT_REG, offs) #define emith_ctx_write(r, offs) \ EOP_STR_IMM(r, CONTEXT_REG, offs) -#define emith_ctx_write_multiple(r, offs, count, tmpr) do { \ - int v_, r_ = r, c_ = count; \ - for (v_ = 0; c_; c_--, r_++) \ - v_ |= 1 << r_; \ - EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2); \ - EOP_STMFD(tmpr,v_); \ +#define emith_ctx_do_multiple(op, r, offs, count, tmpr) do { \ + int v_, r_ = r, c_ = count, b_ = CONTEXT_REG; \ + for (v_ = 0; c_; c_--, r_++) \ + v_ |= 1 << r_; \ + if ((offs) != 0) { \ + EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2);\ + b_ = tmpr; \ + } \ + op(b_,v_); \ } while(0) +#define emith_ctx_read_multiple(r, offs, count, tmpr) \ + emith_ctx_do_multiple(EOP_LDMIA, r, offs, count, tmpr) + +#define emith_ctx_write_multiple(r, offs, count, tmpr) \ + emith_ctx_do_multiple(EOP_STMIA, r, offs, count, tmpr) + #define emith_clear_msb_c(cond, d, s, count) { \ u32 t; \ if ((count) <= 8) { \ @@ -566,22 +633,6 @@ static int emith_xbranch(int cond, void *target, int is_call) EOP_MOV_REG_ASR(d,d,32 - (bits)); \ } -// _r_r -// put bit0 of r0 to carry -#define emith_set_carry(r0) \ - EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \ - -// put bit0 of r0 to carry (for subtraction, inverted on ARM) -#define emith_set_carry_sub(r0) { \ - int t = rcache_get_tmp(); \ - EOP_EOR_IMM(t,r0,0,1); /* invert */ \ - EOP_MOV_REG(A_COND_AL,1,t,t,A_AM1_LSR,1); /* shift out to carry */ \ - rcache_free_tmp(t); \ -} - -#define host_arg2reg(rd, arg) \ - rd = arg - // upto 4 args #define emith_pass_arg_r(arg, reg) \ EOP_MOV_REG_SIMPLE(arg, reg) @@ -589,31 +640,91 @@ static int emith_xbranch(int cond, void *target, int is_call) #define emith_pass_arg_imm(arg, imm) \ emith_move_r_imm(arg, imm) -#define emith_call_cond(cond, target) \ - emith_xbranch(cond, target, 1) +#define emith_jump(target) \ + emith_jump_cond(A_COND_AL, target) + +#define emith_jump_patchable(target) \ + emith_jump(target) #define emith_jump_cond(cond, target) \ emith_xbranch(cond, target, 0) +#define emith_jump_cond_patchable(cond, target) \ + emith_jump_cond(cond, target) + +#define emith_jump_patch(ptr, target) do { \ + u32 *ptr_ = ptr; \ + u32 val_ = (u32 *)(target) - ptr_ - 2; \ + *ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \ +} while (0) + +#define emith_jump_at(ptr, target) { \ + u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \ + EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \ +} + +#define emith_jump_reg_c(cond, r) \ + EOP_C_BX(cond, r) + +#define emith_jump_reg(r) \ + emith_jump_reg_c(A_COND_AL, r) + +#define emith_jump_ctx_c(cond, offs) \ + EOP_LDR_IMM2(cond,15,CONTEXT_REG,offs) + +#define emith_jump_ctx(offs) \ + emith_jump_ctx_c(A_COND_AL, offs) + +#define emith_call_cond(cond, target) \ + emith_xbranch(cond, target, 1) + #define emith_call(target) \ emith_call_cond(A_COND_AL, target) -#define emith_jump(target) \ - emith_jump_cond(A_COND_AL, target) +#define emith_call_ctx(offs) { \ + emith_move_r_r(14, 15); \ + emith_jump_ctx(offs); \ +} -#define emith_jump_reg(r) \ - EOP_BX(r) +#define emith_ret_c(cond) \ + emith_jump_reg_c(cond, 14) + +#define emith_ret() \ + emith_ret_c(A_COND_AL) + +#define emith_ret_to_ctx(offs) \ + emith_ctx_write(14, offs) + +#define emith_push_ret() \ + EOP_STMFD_SP(A_R14M) + +#define emith_pop_and_ret() \ + EOP_LDMFD_SP(A_R15M) + +#define host_instructions_updated(base, end) \ + cache_flush_d_inval_i(base, end) + +#define host_arg2reg(rd, arg) \ + rd = arg /* SH2 drc specific */ +/* pushes r12 for eabi alignment */ #define emith_sh2_drc_entry() \ - EOP_STMFD(13,A_R7M|A_R14M) + EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R14M) #define emith_sh2_drc_exit() \ - EOP_LDMFD(13,A_R7M|A_R15M) - -#define emith_sh2_test_t() { \ - int r = rcache_get_reg(SHR_SR, RC_GR_READ); \ - EOP_TST_IMM(r, 0, 1); \ + EOP_LDMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R12M|A_R15M) + +#define emith_sh2_wcall(a, tab, ret_ptr) { \ + int val_ = (char *)(ret_ptr) - (char *)tcache_ptr - 2*4; \ + if (val_ >= 0) \ + emith_add_r_r_imm(14, 15, val_); \ + else if (val_ < 0) \ + emith_sub_r_r_imm(14, 15, -val_); \ + emith_lsr(12, a, SH2_WRITE_SHIFT); \ + EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \ + emith_ctx_read(2, offsetof(SH2, is_slave)); \ + emith_jump_reg(12); \ } #define emith_sh2_dtbf_loop() { \ @@ -637,11 +748,10 @@ static int emith_xbranch(int cond, void *target, int is_call) rcache_free_tmp(tmp_); \ } -#define emith_write_sr(srcr) { \ - int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \ - emith_lsr(srr, srr, 12); \ - emith_or_r_r_r_lsl(srr, srr, srcr, 20); \ - emith_ror(srr, srr, 20); \ +#define emith_write_sr(sr, srcr) { \ + emith_lsr(sr, sr, 10); \ + emith_or_r_r_r_lsl(sr, sr, srcr, 22); \ + emith_ror(sr, sr, 22); \ } #define emith_carry_to_t(srr, is_sub) { \ @@ -654,6 +764,18 @@ static int emith_xbranch(int cond, void *target, int is_call) } \ } +#define emith_tpop_carry(sr, is_sub) { \ + if (is_sub) \ + emith_eor_r_imm(sr, 1); \ + emith_lsrf(sr, sr, 1); \ +} + +#define emith_tpush_carry(sr, is_sub) { \ + emith_adc_r_r(sr, sr); \ + if (is_sub) \ + emith_eor_r_imm(sr, 1); \ +} + /* * if Q * t = carry(Rn += Rm)