X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_x86.c;h=3624f5c3f1c55cb14d4b430069de5536f583622d;hb=04092e329bbd050073d42defcd609550d8545e74;hp=247d1d6e808fcb8bd5bf2f4f9a05e52050d66a87;hpb=18b9412743dafb4de7a889b4fba7e34f8a1e8b70;p=picodrive.git

diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c
index 247d1d6..3624f5c 100644
--- a/cpu/drc/emit_x86.c
+++ b/cpu/drc/emit_x86.c
@@ -1,6 +1,6 @@
 /*
  * note:
- *  temp registers must be eax-edx due to use of SETcc.
+ *  temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  * note about silly things like emith_eor_r_r_r:
  *  these are here because the compiler was designed
  *  for ARM as it's primary target.
@@ -63,10 +63,10 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define EMIT_SIB(scale,index,base) \
 	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
 
-#define EMIT_OP_MODRM(op,mod,r,rm) { \
+#define EMIT_OP_MODRM(op,mod,r,rm) do { \
 	EMIT_OP(op); \
 	EMIT_MODRM(mod, r, rm); \
-}
+} while (0)
 
 #define JMP8_POS(ptr) \
 	ptr = tcache_ptr; \
@@ -180,13 +180,18 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT(imm, u32); \
 } while (0)
 
-// 2 - adc, 3 - sbb
 #define emith_add_r_imm(r, imm) \
 	emith_arith_r_imm(0, r, imm)
 
 #define emith_or_r_imm(r, imm) \
 	emith_arith_r_imm(1, r, imm)
 
+#define emith_adc_r_imm(r, imm) \
+	emith_arith_r_imm(2, r, imm)
+
+#define emith_sbc_r_imm(r, imm) \
+	emith_arith_r_imm(3, r, imm) // sbb
+
 #define emith_and_r_imm(r, imm) \
 	emith_arith_r_imm(4, r, imm)
 
@@ -219,27 +224,46 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_add_r_imm(r, imm); \
 }
 
-#define emith_or_r_imm_c(cond, r, imm) { \
-	(void)(cond); \
-	emith_or_r_imm(r, imm); \
-}
-
-#define emith_eor_r_imm_c(cond, r, imm) { \
-	(void)(cond); \
-	emith_eor_r_imm(r, imm); \
-}
-
 #define emith_sub_r_imm_c(cond, r, imm) { \
 	(void)(cond); \
 	emith_sub_r_imm(r, imm); \
 }
 
-#define emith_bic_r_imm_c(cond, r, imm) { \
-	(void)(cond); \
-	emith_bic_r_imm(r, imm); \
-}
+#define emith_or_r_imm_c(cond, r, imm) \
+	emith_or_r_imm(r, imm)
+#define emith_eor_r_imm_c(cond, r, imm) \
+	emith_eor_r_imm(r, imm)
+#define emith_bic_r_imm_c(cond, r, imm) \
+	emith_bic_r_imm(r, imm)
+#define emith_ror_c(cond, d, s, cnt) \
+	emith_ror(d, s, cnt)
+
+#define emith_read_r_r_offs_c(cond, r, rs, offs) \
+	emith_read_r_r_offs(r, rs, offs)
+#define emith_write_r_r_offs_c(cond, r, rs, offs) \
+	emith_write_r_r_offs(r, rs, offs)
+#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
+	emith_read8_r_r_offs(r, rs, offs)
+#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
+	emith_write8_r_r_offs(r, rs, offs)
+#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
+	emith_read16_r_r_offs(r, rs, offs)
+#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
+	emith_write16_r_r_offs(r, rs, offs)
+#define emith_jump_reg_c(cond, r) \
+	emith_jump_reg(r)
+#define emith_jump_ctx_c(cond, offs) \
+	emith_jump_ctx(offs)
+#define emith_ret_c(cond) \
+	emith_ret()
 
 // _r_r_imm
+#define emith_add_r_r_imm(d, s, imm) { \
+	if (d != s) \
+		emith_move_r_r(d, s); \
+	emith_add_r_imm(d, imm); \
+}
+
 #define emith_and_r_r_imm(d, s, imm) { \
 	if (d != s) \
 		emith_move_r_r(d, s); \
@@ -279,6 +303,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_push(r) \
 	EMIT_OP(0x50 + (r))
 
+#define emith_push_imm(imm) { \
+	EMIT_OP(0x68); \
+	EMIT(imm, u32); \
+}
+
 #define emith_pop(r) \
 	EMIT_OP(0x58 + (r))
 
@@ -376,35 +405,91 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_rolcf emith_rolc
 #define emith_rorcf emith_rorc
 
-// XXX: offs is 8bit only
-#define emith_ctx_read(r, offs) do { \
-	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
-	EMIT(offs, u8); 	/* mov tmp, [ebp+#offs] */ \
+#define emith_deref_op(op, r, rs, offs) do { \
+	/* mov r <-> [ebp+#offs] */ \
+	if ((offs) >= 0x80) { \
+		EMIT_OP_MODRM(op, 2, r, rs); \
+		EMIT(offs, u32); \
+	} else { \
+		EMIT_OP_MODRM(op, 1, r, rs); \
+		EMIT(offs, u8); \
+	} \
+} while (0)
+
+#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
+
+#define emith_read_r_r_offs(r, rs, offs) \
+	emith_deref_op(0x8b, r, rs, offs)
+
+#define emith_write_r_r_offs(r, rs, offs) \
+	emith_deref_op(0x89, r, rs, offs)
+
+// note: don't use prefixes on this
+#define emith_read8_r_r_offs(r, rs, offs) do { \
+	int r_ = r; \
+	if (!is_abcdx(r)) \
+		r_ = rcache_get_tmp(); \
+	emith_deref_op(0x8a, r_, rs, offs); \
+	if ((r) != r_) { \
+		emith_move_r_r(r, r_); \
+		rcache_free_tmp(r_); \
+	} \
 } while (0)
 
+#define emith_write8_r_r_offs(r, rs, offs) do {\
+	int r_ = r; \
+	if (!is_abcdx(r)) { \
+		r_ = rcache_get_tmp(); \
+		emith_move_r_r(r_, r); \
+	} \
+	emith_deref_op(0x88, r_, rs, offs); \
+	if ((r) != r_) \
+		rcache_free_tmp(r_); \
+} while (0)
+
+#define emith_read16_r_r_offs(r, rs, offs) { \
+	EMIT(0x66, u8); /* operand override */ \
+	emith_read_r_r_offs(r, rs, offs); \
+}
+
+#define emith_write16_r_r_offs(r, rs, offs) { \
+	EMIT(0x66, u8); \
+	emith_write_r_r_offs(r, rs, offs); \
+}
+
+#define emith_ctx_read(r, offs) \
+	emith_read_r_r_offs(r, CONTEXT_REG, offs)
+
+#define emith_ctx_write(r, offs) \
+	emith_write_r_r_offs(r, CONTEXT_REG, offs)
+
 #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
 	int r_ = r, offs_ = offs, cnt_ = cnt;     \
 	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
 		emith_ctx_read(r_, offs_);        \
 } while (0)
 
-#define emith_ctx_write(r, offs) do { \
-	EMIT_OP_MODRM(0x89, 1, r, xBP); \
-	EMIT(offs, u8); 	/* mov [ebp+#offs], tmp */ \
-} while (0)
-
 #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
 	int r_ = r, offs_ = offs, cnt_ = cnt;     \
 	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
 		emith_ctx_write(r_, offs_);       \
 } while (0)
 
+// assumes EBX is free
+#define emith_ret_to_ctx(offs) { \
+	emith_pop(xBX); \
+	emith_ctx_write(xBX, offs); \
+}
+
 #define emith_jump(ptr) { \
 	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
 	EMIT_OP(0xe9); \
 	EMIT(disp, u32); \
 }
 
+#define emith_jump_patchable(target) \
+	emith_jump(target)
+
 #define emith_jump_cond(cond, ptr) { \
 	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
 	EMIT(0x0f, u8); \
@@ -412,14 +497,21 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT(disp, u32); \
 }
 
-#define emith_jump_patchable(cond) \
-	emith_jump_cond(cond, 0)
+#define emith_jump_cond_patchable(cond, target) \
+	emith_jump_cond(cond, target)
 
 #define emith_jump_patch(ptr, target) do { \
-	u32 disp = (u32)(target) - ((u32)(ptr) + 6); \
-	EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \
+	u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
+	u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
+	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
 } while (0)
 
+#define emith_jump_at(ptr, target) { \
+	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
+	EMIT_PTR(ptr, 0xe9, u8); \
+	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
+}
+
 #define emith_call(ptr) { \
 	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
 	EMIT_OP(0xe8); \
@@ -429,9 +521,30 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_call_cond(cond, ptr) \
 	emith_call(ptr)
 
+#define emith_call_reg(r) \
+	EMIT_OP_MODRM(0xff, 3, 2, r)
+
+#define emith_call_ctx(offs) { \
+	EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
+	EMIT(offs, u32); \
+}
+
+#define emith_ret() \
+	EMIT_OP(0xc3)
+
 #define emith_jump_reg(r) \
 	EMIT_OP_MODRM(0xff, 3, 4, r)
 
+#define emith_jump_ctx(offs) { \
+	EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
+	EMIT(offs, u32); \
+}
+
+#define emith_push_ret()
+
+#define emith_pop_and_ret() \
+	emith_ret()
+
 #define EMITH_JMP_START(cond) { \
 	u8 *cond_ptr; \
 	JMP8_POS(cond_ptr)
@@ -440,16 +553,26 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	JMP8_EMIT(cond, cond_ptr); \
 }
 
+#define EMITH_JMP3_START(cond) { \
+	u8 *cond_ptr, *else_ptr; \
+	JMP8_POS(cond_ptr)
+
+#define EMITH_JMP3_MID(cond) \
+	JMP8_POS(else_ptr); \
+	JMP8_EMIT(cond, cond_ptr);
+
+#define EMITH_JMP3_END() \
+	JMP8_EMIT_NC(else_ptr); \
+}
+
 // "simple" jump (no more then a few insns)
+// ARM will use conditional instructions here
 #define EMITH_SJMP_START EMITH_JMP_START
 #define EMITH_SJMP_END EMITH_JMP_END
 
-#define host_arg2reg(rd, arg) \
-	switch (arg) { \
-	case 0: rd = xAX; break; \
-	case 1: rd = xDX; break; \
-	case 2: rd = xCX; break; \
-	}
+#define EMITH_SJMP3_START EMITH_JMP3_START
+#define EMITH_SJMP3_MID EMITH_JMP3_MID
+#define EMITH_SJMP3_END EMITH_JMP3_END
 
 #define emith_pass_arg_r(arg, reg) { \
 	int rd = 7; \
@@ -463,6 +586,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_move_r_imm(rd, imm); \
 }
 
+#define host_instructions_updated(base, end)
+
+#define host_arg2reg(rd, arg) \
+	switch (arg) { \
+	case 0: rd = xAX; break; \
+	case 1: rd = xDX; break; \
+	case 2: rd = xCX; break; \
+	}
+
 /* SH2 drc specific */
 #define emith_sh2_drc_entry() { \
 	emith_push(xBX);        \
@@ -476,7 +608,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_pop(xSI);         \
 	emith_pop(xBP);         \
 	emith_pop(xBX);         \
-	EMIT_OP(0xc3); /* ret */\
+	emith_ret();            \
+}
+
+// assumes EBX is free temporary
+#define emith_sh2_wcall(a, tab, ret_ptr) { \
+	int arg2_; \
+	host_arg2reg(arg2_, 2); \
+	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
+	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
+	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
+	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
+	emith_push_imm((long)(ret_ptr)); \
+	emith_jump_reg(xBX); \
 }
 
 #define emith_sh2_dtbf_loop() { \