X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_x86.c;h=754c27fe1a4c1ef227cf69cdd1bc50936dfcd834;hb=9db6a54485501b56b0f2f5db4d093c38fe495bda;hp=1c29eeafefafa58cdc16d5477543de47b86d56f4;hpb=b081408f66662068a3d274f696bdabba5186b68e;p=picodrive.git diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c index 1c29eea..754c27f 100644 --- a/cpu/drc/emit_x86.c +++ b/cpu/drc/emit_x86.c @@ -1,6 +1,12 @@ /* + * Basic macros to emit x86 instructions and some utils + * Copyright (C) 2008,2009,2010 notaz + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. + * * note: - * temp registers must be eax-edx due to use of SETcc. + * temp registers must be eax-edx due to use of SETcc and r/w 8/16. * note about silly things like emith_eor_r_r_r: * these are here because the compiler was designed * for ARM as it's primary target. @@ -63,10 +69,10 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; #define EMIT_SIB(scale,index,base) \ EMIT(((scale)<<6) | ((index)<<3) | (base), u8) -#define EMIT_OP_MODRM(op,mod,r,rm) { \ +#define EMIT_OP_MODRM(op,mod,r,rm) do { \ EMIT_OP(op); \ EMIT_MODRM(mod, r, rm); \ -} +} while (0) #define JMP8_POS(ptr) \ ptr = tcache_ptr; \ @@ -139,6 +145,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; } // _r_r_r +#define emith_add_r_r_r(d, s1, s2) { \ + if (d == s1) { \ + emith_add_r_r(d, s2); \ + } else if (d == s2) { \ + emith_add_r_r(d, s1); \ + } else { \ + emith_move_r_r(d, s1); \ + emith_add_r_r(d, s2); \ + } \ +} + #define emith_eor_r_r_r(d, s1, s2) { \ if (d == s1) { \ emith_eor_r_r(d, s2); \ @@ -180,13 +197,18 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; EMIT(imm, u32); \ } while (0) -// 2 - adc, 3 - sbb #define emith_add_r_imm(r, imm) \ emith_arith_r_imm(0, r, imm) #define emith_or_r_imm(r, imm) \ emith_arith_r_imm(1, r, imm) +#define emith_adc_r_imm(r, imm) \ + emith_arith_r_imm(2, r, imm) + +#define emith_sbc_r_imm(r, imm) \ + emith_arith_r_imm(3, r, imm) // sbb + #define emith_and_r_imm(r, imm) \ emith_arith_r_imm(4, r, imm) @@ -411,17 +433,36 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; } \ } while (0) +#define is_abcdx(r) (xAX <= (r) && (r) <= xDX) + #define emith_read_r_r_offs(r, rs, offs) \ emith_deref_op(0x8b, r, rs, offs) #define emith_write_r_r_offs(r, rs, offs) \ emith_deref_op(0x89, r, rs, offs) -#define emith_read8_r_r_offs(r, rs, offs) \ - emith_deref_op(0x8a, r, rs, offs) +// note: don't use prefixes on this +#define emith_read8_r_r_offs(r, rs, offs) do { \ + int r_ = r; \ + if (!is_abcdx(r)) \ + r_ = rcache_get_tmp(); \ + emith_deref_op(0x8a, r_, rs, offs); \ + if ((r) != r_) { \ + emith_move_r_r(r, r_); \ + rcache_free_tmp(r_); \ + } \ +} while (0) -#define emith_write8_r_r_offs(r, rs, offs) \ - emith_deref_op(0x88, r, rs, offs) +#define emith_write8_r_r_offs(r, rs, offs) do {\ + int r_ = r; \ + if (!is_abcdx(r)) { \ + r_ = rcache_get_tmp(); \ + emith_move_r_r(r_, r); \ + } \ + emith_deref_op(0x88, r_, rs, offs); \ + if ((r) != r_) \ + rcache_free_tmp(r_); \ +} while (0) #define emith_read16_r_r_offs(r, rs, offs) { \ EMIT(0x66, u8); /* operand override */ \ @@ -430,7 +471,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; #define emith_write16_r_r_offs(r, rs, offs) { \ EMIT(0x66, u8); \ - emith_write16_r_r_offs(r, rs, offs) \ + emith_write_r_r_offs(r, rs, offs); \ } #define emith_ctx_read(r, offs) \ @@ -463,6 +504,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; EMIT(disp, u32); \ } +#define emith_jump_patchable(target) \ + emith_jump(target) + #define emith_jump_cond(cond, ptr) { \ u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \ EMIT(0x0f, u8); \ @@ -470,14 +514,21 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; EMIT(disp, u32); \ } -#define emith_jump_patchable(cond) \ - emith_jump_cond(cond, 0) +#define emith_jump_cond_patchable(cond, target) \ + emith_jump_cond(cond, target) #define emith_jump_patch(ptr, target) do { \ - u32 disp = (u32)(target) - ((u32)(ptr) + 6); \ - EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \ + u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \ + u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \ + EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \ } while (0) +#define emith_jump_at(ptr, target) { \ + u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \ + EMIT_PTR(ptr, 0xe9, u8); \ + EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \ +} + #define emith_call(ptr) { \ u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \ EMIT_OP(0xe8); \ @@ -506,6 +557,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; EMIT(offs, u32); \ } +#define emith_push_ret() + +#define emith_pop_and_ret() \ + emith_ret() + #define EMITH_JMP_START(cond) { \ u8 *cond_ptr; \ JMP8_POS(cond_ptr) @@ -535,13 +591,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; #define EMITH_SJMP3_MID EMITH_JMP3_MID #define EMITH_SJMP3_END EMITH_JMP3_END -#define host_arg2reg(rd, arg) \ - switch (arg) { \ - case 0: rd = xAX; break; \ - case 1: rd = xDX; break; \ - case 2: rd = xCX; break; \ - } - #define emith_pass_arg_r(arg, reg) { \ int rd = 7; \ host_arg2reg(rd, arg); \ @@ -554,6 +603,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; emith_move_r_imm(rd, imm); \ } +#define host_instructions_updated(base, end) + +#define host_arg2reg(rd, arg) \ + switch (arg) { \ + case 0: rd = xAX; break; \ + case 1: rd = xDX; break; \ + case 2: rd = xCX; break; \ + } + /* SH2 drc specific */ #define emith_sh2_drc_entry() { \ emith_push(xBX); \ @@ -571,14 +629,13 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; } // assumes EBX is free temporary -#define emith_sh2_wcall(a, tab, ret_ptr) { \ +#define emith_sh2_wcall(a, tab) { \ int arg2_; \ host_arg2reg(arg2_, 2); \ emith_lsr(xBX, a, SH2_WRITE_SHIFT); \ EMIT_OP_MODRM(0x8b, 0, xBX, 4); \ EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \ - emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \ - emith_push_imm((long)(ret_ptr)); \ + emith_move_r_r(arg2_, CONTEXT_REG); \ emith_jump_reg(xBX); \ }