X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fdrc%2Femit_x86.c;h=8f2861235d16175cd3752d3c22429c16181d410f;hb=8b4f38f4c6977ff80fff0ec92228914fe930e534;hp=e94e685b3bbfc7f9f8e3a28dfa691fd7c64ad803;hpb=80599a42dbc06f3e86a09dae9dc98dccbb84b48c;p=picodrive.git

diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c
index e94e685..8f28612 100644
--- a/cpu/drc/emit_x86.c
+++ b/cpu/drc/emit_x86.c
@@ -1,22 +1,47 @@
+/*
+ * note:
+ *  temp registers must be eax-edx due to use of SETcc.
+ * note about silly things like emith_eor_r_r_r:
+ *  these are here because the compiler was designed
+ *  for ARM as it's primary target.
+ */
 #include <stdarg.h>
 
 enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 
 #define CONTEXT_REG xBP
 
+#define IOP_JMP 0xeb
+#define IOP_JO  0x70
+#define IOP_JNO 0x71
+#define IOP_JB  0x72
+#define IOP_JAE 0x73
 #define IOP_JE  0x74
 #define IOP_JNE 0x75
 #define IOP_JBE 0x76
 #define IOP_JA  0x77
 #define IOP_JS  0x78
 #define IOP_JNS 0x79
+#define IOP_JL  0x7c
+#define IOP_JGE 0x7d
 #define IOP_JLE 0x7e
+#define IOP_JG  0x7f
 
 // unified conditions (we just use rel8 jump instructions for x86)
 #define DCOND_EQ IOP_JE
 #define DCOND_NE IOP_JNE
 #define DCOND_MI IOP_JS      // MInus
 #define DCOND_PL IOP_JNS     // PLus or zero
+#define DCOND_HI IOP_JA      // higher (unsigned)
+#define DCOND_HS IOP_JAE     // higher || same (unsigned)
+#define DCOND_LO IOP_JB      // lower (unsigned)
+#define DCOND_LS IOP_JBE     // lower || same (unsigned)
+#define DCOND_GE IOP_JGE     // greater || equal (signed)
+#define DCOND_GT IOP_JG      // greater (signed)
+#define DCOND_LE IOP_JLE     // less || equal (signed)
+#define DCOND_LT IOP_JL      // less (signed)
+#define DCOND_VS IOP_JO      // oVerflow Set
+#define DCOND_VC IOP_JNO     // oVerflow Clear
 
 #define EMIT_PTR(ptr, val, type) \
 	*(type *)(ptr) = val
@@ -34,6 +59,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define EMIT_MODRM(mod,r,rm) \
 	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
 
+#define EMIT_SIB(scale,index,base) \
+	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
+
 #define EMIT_OP_MODRM(op,mod,r,rm) { \
 	EMIT_OP(op); \
 	EMIT_MODRM(mod, r, rm); \
@@ -47,6 +75,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT_PTR(ptr, op, u8); \
 	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
 
+// _r_r
 #define emith_move_r_r(dst, src) \
 	EMIT_OP_MODRM(0x8b, 3, dst, src)
 
@@ -56,11 +85,26 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_sub_r_r(d, s) \
 	EMIT_OP_MODRM(0x29, 3, s, d)
 
+#define emith_adc_r_r(d, s) \
+	EMIT_OP_MODRM(0x11, 3, s, d)
+
+#define emith_sbc_r_r(d, s) \
+	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
+
 #define emith_or_r_r(d, s) \
 	EMIT_OP_MODRM(0x09, 3, s, d)
 
+#define emith_and_r_r(d, s) \
+	EMIT_OP_MODRM(0x21, 3, s, d)
+
 #define emith_eor_r_r(d, s) \
-	EMIT_OP_MODRM(0x31, 3, s, d)
+	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
+
+#define emith_tst_r_r(d, s) \
+	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
+
+#define emith_cmp_r_r(d, s) \
+	EMIT_OP_MODRM(0x39, 3, s, d)
 
 // fake teq - test equivalence - get_flags(d ^ s)
 #define emith_teq_r_r(d, s) { \
@@ -69,18 +113,69 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_pop(d); \
 }
 
+#define emith_mvn_r_r(d, s) { \
+	if (d != s) \
+		emith_move_r_r(d, s); \
+	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
+}
+
+#define emith_negc_r_r(d, s) { \
+	int tmp_ = rcache_get_tmp(); \
+	emith_move_r_imm(tmp_, 0); \
+	emith_sbc_r_r(tmp_, s); \
+	emith_move_r_r(d, tmp_); \
+	rcache_free_tmp(tmp_); \
+}
+
+#define emith_neg_r_r(d, s) { \
+	if (d != s) \
+		emith_move_r_r(d, s); \
+	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
+}
+
+// _r_r_r
+#define emith_eor_r_r_r(d, s1, s2) { \
+	if (d == s1) { \
+		emith_eor_r_r(d, s2); \
+	} else if (d == s2) { \
+		emith_eor_r_r(d, s1); \
+	} else { \
+		emith_move_r_r(d, s1); \
+		emith_eor_r_r(d, s2); \
+	} \
+}
+
+// _r_r_shift
+#define emith_or_r_r_lsl(d, s, lslimm) { \
+	int tmp_ = rcache_get_tmp(); \
+	emith_lsl(tmp_, s, lslimm); \
+	emith_or_r_r(d, tmp_); \
+	rcache_free_tmp(tmp_); \
+}
+
+// d != s
+#define emith_eor_r_r_lsr(d, s, lsrimm) { \
+	emith_push(s); \
+	emith_lsr(s, s, lsrimm); \
+	emith_eor_r_r(d, s); \
+	emith_pop(s); \
+}
+
 // _r_imm
 #define emith_move_r_imm(r, imm) { \
 	EMIT_OP(0xb8 + (r)); \
 	EMIT(imm, u32); \
 }
 
+#define emith_move_r_imm_s8(r, imm) \
+	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
+
 #define emith_arith_r_imm(op, r, imm) { \
 	EMIT_OP_MODRM(0x81, 3, op, r); \
 	EMIT(imm, u32); \
 }
 
-// 2 - adc, 3 - sbb, 6 - xor, 7 - cmp
+// 2 - adc, 3 - sbb
 #define emith_add_r_imm(r, imm) \
 	emith_arith_r_imm(0, r, imm)
 
@@ -93,6 +188,12 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define emith_sub_r_imm(r, imm) \
 	emith_arith_r_imm(5, r, imm)
 
+#define emith_eor_r_imm(r, imm) \
+	emith_arith_r_imm(6, r, imm)
+
+#define emith_cmp_r_imm(r, imm) \
+	emith_arith_r_imm(7, r, imm)
+
 #define emith_tst_r_imm(r, imm) { \
 	EMIT_OP_MODRM(0xf7, 3, 0, r); \
 	EMIT(imm, u32); \
@@ -103,19 +204,41 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_arith_r_imm(4, r, ~(imm))
 
 // fake conditionals (using SJMP instead)
+#define emith_move_r_imm_c(cond, r, imm) { \
+	(void)(cond); \
+	emith_move_r_imm(r, imm); \
+}
+
 #define emith_add_r_imm_c(cond, r, imm) { \
 	(void)(cond); \
-	emith_arith_r_imm(0, r, imm); \
+	emith_add_r_imm(r, imm); \
 }
 
 #define emith_or_r_imm_c(cond, r, imm) { \
 	(void)(cond); \
-	emith_arith_r_imm(1, r, imm); \
+	emith_or_r_imm(r, imm); \
+}
+
+#define emith_eor_r_imm_c(cond, r, imm) { \
+	(void)(cond); \
+	emith_eor_r_imm(r, imm); \
 }
 
 #define emith_sub_r_imm_c(cond, r, imm) { \
 	(void)(cond); \
-	emith_arith_r_imm(5, r, imm); \
+	emith_sub_r_imm(r, imm); \
+}
+
+#define emith_bic_r_imm_c(cond, r, imm) { \
+	(void)(cond); \
+	emith_bic_r_imm(r, imm); \
+}
+
+// _r_r_imm
+#define emith_and_r_r_imm(d, s, imm) { \
+	if (d != s) \
+		emith_move_r_r(d, s); \
+	emith_and_r_imm(d, imm) \
 }
 
 // shift
@@ -126,11 +249,26 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT(cnt, u8); \
 }
 
+#define emith_lsl(d, s, cnt) \
+	emith_shift(4, d, s, cnt)
+
+#define emith_lsr(d, s, cnt) \
+	emith_shift(5, d, s, cnt)
+
 #define emith_asr(d, s, cnt) \
 	emith_shift(7, d, s, cnt)
 
-#define emith_lsl(d, s, cnt) \
-	emith_shift(4, d, s, cnt)
+#define emith_rol(d, s, cnt) \
+	emith_shift(0, d, s, cnt)
+
+#define emith_ror(d, s, cnt) \
+	emith_shift(1, d, s, cnt)
+
+#define emith_rolc(r) \
+	EMIT_OP_MODRM(0xd1, 3, 2, r)
+
+#define emith_rorc(r) \
+	EMIT_OP_MODRM(0xd1, 3, 3, r)
 
 // misc
 #define emith_push(r) \
@@ -150,16 +288,28 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_and_r_imm(d, t); \
 }
 
+#define emith_clear_msb_c(cond, d, s, count) { \
+	(void)(cond); \
+	emith_clear_msb(d, s, count); \
+}
+
 #define emith_sext(d, s, bits) { \
 	emith_lsl(d, s, 32 - (bits)); \
 	emith_asr(d, d, 32 - (bits)); \
 }
 
+#define emith_setc(r) { \
+	EMIT_OP(0x0f); \
+	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
+}
+
 // XXX: stupid mess
-#define emith_mul(d, s1, s2) { \
+#define emith_mul_(op, dlo, dhi, s1, s2) { \
 	int rmr; \
-	if (d != xAX) \
+	if (dlo != xAX && dhi != xAX) \
 		emith_push(xAX); \
+	if (dlo != xDX && dhi != xDX) \
+		emith_push(xDX); \
 	if ((s1) == xAX) \
 		rmr = s2; \
 	else if ((s2) == xAX) \
@@ -168,29 +318,81 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 		emith_move_r_r(xAX, s1); \
 		rmr = s2; \
 	} \
-	emith_push(xDX); \
-	EMIT_OP_MODRM(0xf7, 3, 4, rmr); /* MUL rmr */ \
-	emith_pop(xDX); \
-	if (d != xAX) { \
-		emith_move_r_r(d, xAX); \
+	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
+	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
+	if (dhi != xDX && dhi != -1) \
+		emith_push(xDX); \
+	if (dlo != xAX) \
+		emith_move_r_r(dlo, xAX); \
+	if (dhi != xDX && dhi != -1) \
+		emith_pop(dhi); \
+	if (dlo != xDX && dhi != xDX) \
+		emith_pop(xDX); \
+	if (dlo != xAX && dhi != xAX) \
 		emith_pop(xAX); \
-	} \
+}
+
+#define emith_mul_u64(dlo, dhi, s1, s2) \
+	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
+
+#define emith_mul_s64(dlo, dhi, s1, s2) \
+	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
+
+#define emith_mul(d, s1, s2) \
+	emith_mul_(4, d, -1, s1, s2)
+
+// (dlo,dhi) += signed(s1) * signed(s2)
+#define emith_mula_s64(dlo, dhi, s1, s2) { \
+	emith_push(dhi); \
+	emith_push(dlo); \
+	emith_mul_(5, dlo, dhi, s1, s2); \
+	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
+	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
+	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
+	EMIT_SIB(0, 4, 4); \
+	EMIT(4, u8); /* adc dhi, [esp+4] */ \
+	emith_add_r_imm(xSP, 4*2); \
 }
 
 // "flag" instructions are the same
 #define emith_subf_r_imm emith_sub_r_imm
+#define emith_addf_r_r   emith_add_r_r
 #define emith_subf_r_r   emith_sub_r_r
+#define emith_adcf_r_r   emith_adc_r_r
+#define emith_sbcf_r_r   emith_sbc_r_r
+#define emith_eorf_r_r   emith_eor_r_r
+#define emith_negcf_r_r  emith_negc_r_r
+
+#define emith_lslf  emith_lsl
+#define emith_lsrf  emith_lsr
+#define emith_asrf  emith_asr
+#define emith_rolf  emith_rol
+#define emith_rorf  emith_ror
+#define emith_rolcf emith_rolc
+#define emith_rorcf emith_rorc
 
 // XXX: offs is 8bit only
-#define emith_ctx_read(r, offs) { \
+#define emith_ctx_read(r, offs) do { \
 	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
 	EMIT(offs, u8); 	/* mov tmp, [ebp+#offs] */ \
-}
+} while (0)
+
+#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
+	int r_ = r, offs_ = offs, cnt_ = cnt;     \
+	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+		emith_ctx_read(r_, offs_);        \
+} while (0)
 
-#define emith_ctx_write(r, offs) { \
+#define emith_ctx_write(r, offs) do { \
 	EMIT_OP_MODRM(0x89, 1, r, xBP); \
 	EMIT(offs, u8); 	/* mov [ebp+#offs], tmp */ \
-}
+} while (0)
+
+#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
+	int r_ = r, offs_ = offs, cnt_ = cnt;     \
+	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
+		emith_ctx_write(r_, offs_);       \
+} while (0)
 
 #define emith_jump(ptr) { \
 	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
@@ -204,15 +406,24 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT(disp, u32); \
 }
 
-// "simple" or "short" jump
-#define EMITH_SJMP_START(cond) { \
+#define emith_call_cond(cond, ptr) \
+	emith_call(ptr)
+
+#define emith_jump_reg(r) \
+	EMIT_OP_MODRM(0xff, 3, 4, r)
+
+#define EMITH_JMP_START(cond) { \
 	u8 *cond_ptr; \
 	JMP8_POS(cond_ptr)
 
-#define EMITH_SJMP_END(cond) \
+#define EMITH_JMP_END(cond) \
 	JMP8_EMIT(cond, cond_ptr); \
 }
 
+// "simple" jump (no more then a few insns)
+#define EMITH_SJMP_START EMITH_JMP_START
+#define EMITH_SJMP_END EMITH_JMP_END
+
 #define host_arg2reg(rd, arg) \
 	switch (arg) { \
 	case 0: rd = xAX; break; \
@@ -233,28 +444,44 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 }
 
 /* SH2 drc specific */
+#define emith_sh2_drc_entry() { \
+	emith_push(xBX);        \
+	emith_push(xBP);        \
+	emith_push(xSI);        \
+	emith_push(xDI);        \
+}
+
+#define emith_sh2_drc_exit() {  \
+	emith_pop(xDI);         \
+	emith_pop(xSI);         \
+	emith_pop(xBP);         \
+	emith_pop(xBX);         \
+	EMIT_OP(0xc3); /* ret */\
+}
+
 #define emith_sh2_test_t() { \
 	int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
-	EMIT_OP_MODRM(0xf6, 3, 0, t); \
-	EMIT(0x01, u8); /* test <reg>, byte 1 */ \
+	EMIT(0x66, u8); \
+	EMIT_OP_MODRM(0xf7, 3, 0, t); \
+	EMIT(0x01, u16); /* test <reg>, word 1 */ \
 }
 
 #define emith_sh2_dtbf_loop() { \
 	u8 *jmp0; /* negative cycles check */            \
 	u8 *jmp1; /* unsinged overflow check */          \
 	int cr, rn;                                      \
-	tmp = rcache_get_tmp();                          \
+	int tmp_ = rcache_get_tmp();                     \
 	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
 	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
 	emith_sub_r_imm(rn, 1);                          \
 	emith_sub_r_imm(cr, (cycles+1) << 12);           \
 	cycles = 0;                                      \
-	emith_asr(tmp, cr, 2+12);                        \
+	emith_asr(tmp_, cr, 2+12);                       \
 	JMP8_POS(jmp0); /* no negative cycles */         \
-	emith_move_r_imm(tmp, 0);                        \
+	emith_move_r_imm(tmp_, 0);                       \
 	JMP8_EMIT(IOP_JNS, jmp0);                        \
 	emith_and_r_imm(cr, 0xffe);                      \
-	emith_subf_r_r(rn, tmp);                         \
+	emith_subf_r_r(rn, tmp_);                        \
 	JMP8_POS(jmp1); /* no overflow */                \
 	emith_neg_r(rn); /* count left */                \
 	emith_lsl(rn, rn, 2+12);                         \
@@ -262,6 +489,44 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_or_r_imm(cr, 1);                           \
 	emith_move_r_imm(rn, 0);                         \
 	JMP8_EMIT(IOP_JA, jmp1);                         \
-	rcache_free_tmp(tmp);                            \
+	rcache_free_tmp(tmp_);                           \
+}
+
+#define emith_write_sr(srcr) { \
+	int tmp_ = rcache_get_tmp(); \
+	int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
+	emith_clear_msb(tmp_, srcr, 20); \
+	emith_bic_r_imm(srr, 0xfff); \
+	emith_or_r_r(srr, tmp_); \
+	rcache_free_tmp(tmp_); \
+}
+
+#define emith_tpop_carry(sr, is_sub) \
+	emith_lsr(sr, sr, 1)
+
+#define emith_tpush_carry(sr, is_sub) \
+	emith_adc_r_r(sr, sr)
+
+/*
+ * if Q
+ *   t = carry(Rn += Rm)
+ * else
+ *   t = carry(Rn -= Rm)
+ * T ^= t
+ */
+#define emith_sh2_div1_step(rn, rm, sr) {         \
+	u8 *jmp0, *jmp1;                          \
+	int tmp_ = rcache_get_tmp();              \
+	emith_eor_r_r(tmp_, tmp_);                \
+	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
+	JMP8_POS(jmp0);          /* je do_sub */  \
+	emith_add_r_r(rn, rm);                    \
+	JMP8_POS(jmp1);          /* jmp done */   \
+	JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */    \
+	emith_sub_r_r(rn, rm);                    \
+	JMP8_EMIT(IOP_JMP, jmp1);/* done: */      \
+	emith_setc(tmp_);                         \
+	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
+	rcache_free_tmp(tmp_);                    \
 }