X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fsh2%2Fcompiler.c;h=0e8b65b39de2545589a18478445d00f9ba506243;hb=d602fd4f739acca7145b4208134da15fad2a6c6e;hp=e9838978ee6cf2833b81d56c986d513f6932bd60;hpb=2dbc96b1c783a2cb147321f6131d67691d36e592;p=picodrive.git diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index e983897..0e8b65b 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -47,10 +47,11 @@ #define MAX_LOCAL_BRANCHES 32 // debug stuff -// 1 - warnings/errors -// 2 - block info/smc -// 4 - asm -// 8 - runtime block entry log +// 01 - warnings/errors +// 02 - block info/smc +// 04 - asm +// 08 - runtime block entry log +// 10 - smc self-check // { #ifndef DRC_DEBUG #define DRC_DEBUG 0 @@ -349,7 +350,7 @@ static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2); static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2); static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d); static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); -static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2); +static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2); // address space stuff static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) @@ -363,6 +364,7 @@ static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) } else if ((a & 0xfffff000) == 0xc0000000) { // data array + // FIXME: access sh2->data_array instead poffs = offsetof(SH2, p_da); *mask = 0xfff; } @@ -418,7 +420,7 @@ static void add_to_block_list(struct block_list **blist, struct block_desc *bloc static void rm_from_block_list(struct block_list **blist, struct block_desc *block) { struct block_list *prev = NULL, *current = *blist; - for (; current != NULL; prev = current, current = current->next) { + for (; current != NULL; current = current->next) { if (current->block == block) { if (prev == NULL) *blist = current->next; @@ -427,6 +429,7 @@ static void rm_from_block_list(struct block_list **blist, struct block_desc *blo free(current); return; } + prev = current; } dbg(1, "can't rm block %p (%08x-%08x)", block, block->addr, block->addr + block->size); @@ -513,6 +516,29 @@ missing: dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc); } +static void unregister_links(struct block_entry *be, int tcache_id) +{ + struct block_link *bl_unresolved = unresolved_links[tcache_id]; + struct block_link *bl, *bl_next; + + for (bl = be->links; bl != NULL; ) { + bl_next = bl->next; + bl->next = bl_unresolved; + bl_unresolved = bl; + bl = bl_next; + } + be->links = NULL; + unresolved_links[tcache_id] = bl_unresolved; +} + +// unlike sh2_smc_rm_block, the block stays and can still be accessed +// by other already directly linked blocks, just not preferred +static void kill_block_entry(struct block_entry *be, int tcache_id) +{ + rm_from_hashlist(be, tcache_id); + unregister_links(be, tcache_id); +} + static struct block_desc *dr_add_block(u32 addr, u16 size_lit, u16 size_nolit, int is_slave, int *blk_id) { @@ -523,8 +549,10 @@ static struct block_desc *dr_add_block(u32 addr, u16 size_lit, // do a lookup to get tcache_id and override check be = dr_get_entry(addr, is_slave, &tcache_id); - if (be != NULL) - dbg(1, "block override for %08x", addr); + if (be != NULL) { + dbg(1, "block override for %08x, was %p", addr, be->tcache_ptr); + kill_block_entry(be, tcache_id); + } bcount = &block_counts[tcache_id]; if (*bcount >= block_max_counts[tcache_id]) { @@ -1016,7 +1044,8 @@ static void rcache_unlock_all(void) reg_temp[i].flags &= ~HRF_LOCKED; } -static inline u32 rcache_used_hreg_mask(void) +#ifdef DRC_CMP +static u32 rcache_used_hreg_mask(void) { u32 mask = 0; int i; @@ -1027,6 +1056,7 @@ static inline u32 rcache_used_hreg_mask(void) return mask; } +#endif static void rcache_clean(void) { @@ -1109,8 +1139,11 @@ static void emit_or_t_if_eq(int srr) // reg cache must be clean before call static int emit_memhandler_read_(int size, int ram_check) { - int arg0, arg1; + int arg1; +#if 0 + int arg0; host_arg2reg(arg0, 0); +#endif rcache_clean(); @@ -1227,7 +1260,7 @@ static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int siz return hr2; } -static void emit_memhandler_write(int size, u32 pc) +static void emit_memhandler_write(int size) { int ctxr; host_arg2reg(ctxr, 2); @@ -1474,13 +1507,22 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) // make block entry v = block->entry_count; - if (v < ARRAY_SIZE(block->entryp)) { + if (v < ARRAY_SIZE(block->entryp)) + { + struct block_entry *be_old; + block->entryp[v].pc = pc; block->entryp[v].tcache_ptr = tcache_ptr; block->entryp[v].links = NULL; #if (DRC_DEBUG & 2) block->entryp[v].block = block; #endif + be_old = dr_get_entry(pc, sh2->is_slave, &tcache_id); + if (be_old != NULL) { + dbg(1, "entry override for %08x, was %p", pc, be_old->tcache_ptr); + kill_block_entry(be_old, tcache_id); + } + add_to_hashlist(&block->entryp[v], tcache_id); block->entry_count++; @@ -1508,6 +1550,22 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emit_move_r_imm32(SHR_PC, pc); rcache_clean(); +#if (DRC_DEBUG & 0x10) + rcache_get_reg_arg(0, SHR_PC); + tmp = emit_memhandler_read(2); + tmp2 = rcache_get_tmp(); + tmp3 = rcache_get_tmp(); + emith_move_r_imm(tmp2, FETCH32(pc)); + emith_move_r_imm(tmp3, 0); + emith_cmp_r_r(tmp, tmp2); + EMITH_SJMP_START(DCOND_EQ); + emith_read_r_r_offs_c(DCOND_NE, tmp3, tmp3, 0); // crash + EMITH_SJMP_END(DCOND_EQ); + rcache_free_tmp(tmp); + rcache_free_tmp(tmp2); + rcache_free_tmp(tmp3); +#endif + // check cycles sr = rcache_get_reg(SHR_SR, RC_GR_READ); emith_cmp_r_imm(sr, 0); @@ -1551,8 +1609,8 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) if (delay_dep_bk & BITMASK1(SHR_PC)) { if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) { // can only be those 2 really.. - elprintf(EL_ANOMALY, "%csh2 drc: illegal slot insn %04x @ %08x?", - sh2->is_slave ? 's' : 'm', op, pc - 2); + elprintf_sh2(sh2, EL_ANOMALY, + "drc: illegal slot insn %04x @ %08x?", op, pc - 2); } if (opd->imm != 0) ; // addr already resolved somehow @@ -1717,7 +1775,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(0, SHR_R0); tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ); emith_add_r_r(tmp2, tmp3); - emit_memhandler_write(op & 3, pc); + emit_memhandler_write(op & 3); goto end_op; case 0x07: // MUL.L Rm,Rn 0000nnnnmmmm0111 @@ -1836,7 +1894,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(1, GET_Rm()); if (op & 0x0f) emith_add_r_imm(tmp, (op & 0x0f) * 4); - emit_memhandler_write(2, pc); + emit_memhandler_write(2); goto end_op; case 0x02: @@ -1848,7 +1906,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(1, GET_Rm()); - emit_memhandler_write(op & 3, pc); + emit_memhandler_write(op & 3); goto end_op; case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101 @@ -1858,7 +1916,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_sub_r_imm(tmp, (1 << (op & 3))); rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); - emit_memhandler_write(op & 3, pc); + emit_memhandler_write(op & 3); goto end_op; case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); @@ -2167,7 +2225,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg_arg(1, tmp); if (tmp == SHR_SR) emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0 - emit_memhandler_write(2, pc); + emit_memhandler_write(2); goto end_op; case 0x04: case 0x05: @@ -2307,7 +2365,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_move_r_r(tmp2, tmp); rcache_free_tmp(tmp); rcache_get_reg_arg(0, GET_Rn()); - emit_memhandler_write(0, pc); + emit_memhandler_write(0); break; default: goto default_; @@ -2467,7 +2525,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = (op & 0x100) >> 8; if (op & 0x0f) emith_add_r_imm(tmp, (op & 0x0f) << tmp3); - emit_memhandler_write(tmp3, pc); + emit_memhandler_write(tmp3); goto end_op; case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd @@ -2500,7 +2558,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(1, SHR_R0); tmp3 = (op & 0x300) >> 8; emith_add_r_imm(tmp, (op & 0xff) << tmp3); - emit_memhandler_write(tmp3, pc); + emit_memhandler_write(tmp3); goto end_op; case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd @@ -2516,12 +2574,12 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_add_r_imm(tmp, 4); tmp = rcache_get_reg_arg(1, SHR_SR); emith_clear_msb(tmp, tmp, 22); - emit_memhandler_write(2, pc); + emit_memhandler_write(2); // push PC rcache_get_reg_arg(0, SHR_SP); tmp = rcache_get_tmp_arg(1); emith_move_r_imm(tmp, pc); - emit_memhandler_write(2, pc); + emit_memhandler_write(2); // obtain new PC emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2); // indirect jump -> back to dispatcher @@ -2573,7 +2631,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg_arg(0, SHR_GBR); tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ); emith_add_r_r(tmp3, tmp4); - emit_memhandler_write(0, pc); + emit_memhandler_write(0); goto end_op; } goto default_; @@ -2586,8 +2644,34 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) default: default_: - elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", - sh2->is_slave ? 's' : 'm', op, pc - 2); + if (!(op_flags[i] & OF_B_IN_DS)) + elprintf_sh2(sh2, EL_ANOMALY, + "drc: illegal op %04x @ %08x", op, pc - 2); + + tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); + emith_sub_r_imm(tmp, 4*2); + // push SR + tmp = rcache_get_reg_arg(0, SHR_SP); + emith_add_r_imm(tmp, 4); + tmp = rcache_get_reg_arg(1, SHR_SR); + emith_clear_msb(tmp, tmp, 22); + emit_memhandler_write(2); + // push PC + rcache_get_reg_arg(0, SHR_SP); + tmp = rcache_get_tmp_arg(1); + if (drcf.pending_branch_indirect) { + tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ); + emith_move_r_r(tmp, tmp2); + } + else + emith_move_r_imm(tmp, pc - 2); + emit_memhandler_write(2); + // obtain new PC + v = (op_flags[i] & OF_B_IN_DS) ? 6 : 4; + emit_memhandler_read_rr(SHR_PC, SHR_VBR, v * 4, 2); + // indirect jump -> back to dispatcher + rcache_flush(); + emith_jump(sh2_drc_dispatcher); break; } @@ -2960,13 +3044,12 @@ static void sh2_generate_utils(void) #endif } -static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask) +static void sh2_smc_rm_block(struct block_desc *bd, int tcache_id, u32 ram_mask) { - struct block_link *bl, *bl_next, *bl_unresolved; u32 i, addr, end_addr; void *tmp; - dbg(2, " killing entry %08x-%08x-%08x, blkid %d,%d", + dbg(2, " killing block %08x-%08x-%08x, blkid %d,%d", bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size, tcache_id, bd - block_tables[tcache_id]); if (bd->addr == 0 || bd->entry_count == 0) { @@ -2983,7 +3066,6 @@ static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram } tmp = tcache_ptr; - bl_unresolved = unresolved_links[tcache_id]; // remove from hash table, make incoming links unresolved // XXX: maybe patch branches w/flush instead? @@ -2999,41 +3081,48 @@ static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr); - for (bl = bd->entryp[i].links; bl != NULL; ) { - bl_next = bl->next; - bl->next = bl_unresolved; - bl_unresolved = bl; - bl = bl_next; - } + unregister_links(&bd->entryp[i], tcache_id); } tcache_ptr = tmp; - unresolved_links[tcache_id] = bl_unresolved; bd->addr = bd->size = bd->size_nolit = 0; bd->entry_count = 0; } -static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask) +/* +04205:243: == msh2 block #0,200 060017a8-060017f0 -> 0x27cb9c + 060017a8 d11c MOV.L @($70,PC),R1 ; @$0600181c + +04230:261: msh2 xsh w32 [260017a8] d225e304 +04230:261: msh2 smc check @260017a8 +04239:226: = ssh2 enter 060017a8 0x27cb9c, c=173 +*/ +static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask) { struct block_list **blist = NULL, *entry; - u32 from = ~0, to = 0, end_addr, taddr, i; struct block_desc *block; + u32 start_addr, end_addr, taddr, i; + u32 from = ~0, to = 0; + + // ignore cache-through + a &= ~0x20000000; blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE]; entry = *blist; while (entry != NULL) { block = entry->block; - end_addr = block->addr + block->size; - if (block->addr <= a && a < end_addr) { + start_addr = block->addr & ~0x20000000; + end_addr = start_addr + block->size; + if (start_addr <= a && a < end_addr) { // get addr range that includes all removed blocks - if (from > block->addr) - from = block->addr; + if (from > start_addr) + from = start_addr; if (to < end_addr) to = end_addr; - sh2_smc_rm_block_entry(block, tcache_id, mask); - if (a >= block->addr + block->size_nolit) + sh2_smc_rm_block(block, tcache_id, mask); + if (a >= start_addr + block->size_nolit) literal_disabled_frames = 3; // entry lost, restart search @@ -3056,12 +3145,13 @@ static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, for (; entry != NULL; entry = entry->next) { block = entry->block; - if (block->addr > a) { - if (to > block->addr) - to = block->addr; + start_addr = block->addr & ~0x20000000; + if (start_addr > a) { + if (to > start_addr) + to = start_addr; } else { - end_addr = block->addr + block->size; + end_addr = start_addr + block->size; if (from < end_addr) from = end_addr; } @@ -3078,22 +3168,20 @@ static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) { dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); - sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff); + sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff); } void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) { dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); - sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid], + sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid], 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff); } -int sh2_execute(SH2 *sh2c, int cycles) +int sh2_execute_drc(SH2 *sh2c, int cycles) { int ret_cycles; - sh2c->cycles_timeslice = cycles; - // cycles are kept in SHR_SR unused bits (upper 20) // bit11 contains T saved for delay slot // others are usual SH2 flags @@ -3106,7 +3194,8 @@ int sh2_execute(SH2 *sh2c, int cycles) if (ret_cycles > 0) dbg(1, "warning: drc returned with cycles: %d", ret_cycles); - return sh2c->cycles_timeslice - ret_cycles; + sh2c->sr &= 0x3f3; + return ret_cycles; } #if (DRC_DEBUG & 2) @@ -3158,8 +3247,8 @@ void sh2_drc_flush_all(void) void sh2_drc_mem_setup(SH2 *sh2) { // fill the convenience pointers - sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; - sh2->p_da = Pico32xMem->data_array[sh2->is_slave]; + sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w; + sh2->p_da = sh2->data_array; sh2->p_sdram = Pico32xMem->sdram; sh2->p_rom = Pico.rom; } @@ -3272,12 +3361,12 @@ static void *dr_get_pc_base(u32 pc, int is_slave) if ((pc & ~0x7ff) == 0) { // BIOS - ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; + ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w; mask = 0x7ff; } else if ((pc & 0xfffff000) == 0xc0000000) { // data array - ret = Pico32xMem->data_array[is_slave]; + ret = sh2s[is_slave].data_array; mask = 0xfff; } else if ((pc & 0xc6000000) == 0x06000000) { @@ -3287,7 +3376,8 @@ static void *dr_get_pc_base(u32 pc, int is_slave) } else if ((pc & 0xc6000000) == 0x02000000) { // ROM - ret = Pico.rom; + if ((pc & 0x3fffff) < Pico.romsize) + ret = Pico.rom; mask = 0x3fffff; } @@ -4039,6 +4129,22 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out, is_slave ? 's' : 'm', op, pc); break; } + + if (op_flags[i] & OF_DELAY_OP) { + switch (opd->op) { + case OP_BRANCH: + case OP_BRANCH_CT: + case OP_BRANCH_CF: + case OP_BRANCH_R: + case OP_BRANCH_RF: + elprintf(EL_ANOMALY, "%csh2 drc: branch in DS @ %08x", + is_slave ? 's' : 'm', pc); + opd->op = OP_UNHANDLED; + op_flags[i] |= OF_B_IN_DS; + next_is_delay = 0; + break; + } + } } i_end = i; end_pc = pc;