X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fsh2%2Fcompiler.c;h=336b1facca7114ba1e51056078ede12c0ded350c;hb=ed8cf79be872855234b457ed987d15a2ae1a0ba2;hp=43ca7b7c36adbff8f198e7b21bcea19f2558919f;hpb=80599a42dbc06f3e86a09dae9dc98dccbb84b48c;p=picodrive.git diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index 43ca7b7..336b1fa 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -75,7 +75,7 @@ typedef struct { } temp_reg_t; // note: reg_temp[] must have at least the amount of -// registers used by handlers in worst case (currently 3?) +// registers used by handlers in worst case (currently 4) #ifdef ARM #include "../drc/emit_arm.c" @@ -109,9 +109,10 @@ static const int reg_map_g2h[] = { -1, -1, -1, -1, }; -// ax, cx, dx are usually temporaries +// ax, cx, dx are usually temporaries by convention static temp_reg_t reg_temp[] = { { xAX, }, + { xBX, }, { xCX, }, { xDX, }, }; @@ -509,57 +510,25 @@ MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd SWAP.B Rm,Rn 0110nnnnmmmm1000 SWAP.W Rm,Rn 0110nnnnmmmm1001 -XTRCT Rm,Rn 0010nnnnmmmm1101 -ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii -ADDC Rm,Rn 0011nnnnmmmm1110 -ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii -CMP/EQ Rm,Rn 0011nnnnmmmm0000 -CMP/HS Rm,Rn 0011nnnnmmmm0010 -CMP/GE Rm,Rn 0011nnnnmmmm0011 -CMP/HI Rm,Rn 0011nnnnmmmm0110 -CMP/GT Rm,Rn 0011nnnnmmmm0111 -CMP/PZ Rn 0100nnnn00010001 -CMP/PL Rn 0100nnnn00010101 -CMP/ST Rm,Rn 0010nnnnmmmm1100 -DIV1 Rm,Rn 0011nnnnmmmm0100 -DMULS. Rm,Rn 0011nnnnmmmm1101 -DMULU.L Rm,Rn 0011nnnnmmmm0101 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC @Rm+,@Rn+ 0100nnnnmmmm1111 -MULS.W Rm,Rn 0010nnnnmmmm1111 -MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 -SUB Rm,Rn 0011nnnnmmmm1000 -SUBC Rm,Rn 0011nnnnmmmm1010 -SUBV Rm,Rn 0011nnnnmmmm1011 -AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0,GBR) 11001101iiiiiiii NOT Rm,Rn 0110nnnnmmmm0111 -OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0,GBR) 11001111iiiiiiii TAS.B @Rn 0100nnnn00011011 -TST Rm,Rn 0010nnnnmmmm1000 TST #imm,R0 11001000iiiiiiii TST.B #imm,@(R0,GBR) 11001100iiiiiiii -XOR Rm,Rn 0010nnnnmmmm1010 XOR #imm,R0 11001010iiiiiiii XOR.B #imm,@(R0,GBR) 11001110iiiiiiii -ROTL Rn 0100nnnn00000100 -ROTR Rn 0100nnnn00000101 -ROTCL Rn 0100nnnn00100100 -ROTCR Rn 0100nnnn00100101 -SHAL Rn 0100nnnn00100000 -SHAR Rn 0100nnnn00100001 -SHLL Rn 0100nnnn00000000 -SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 @@ -568,20 +537,9 @@ SHLL16 Rn 0100nnnn00101000 SHLR16 Rn 0100nnnn00101001 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 -LDC.L @Rm+,GBR 0100mmmm00010111 -LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 -LDS.L @Rm+,MACH 0100mmmm00000110 -LDS.L @Rm+,MACL 0100mmmm00010110 -LDS.L @Rm+,PR 0100mmmm00100110 -STC.L SR,@–Rn 0100nnnn00000011 -STC.L GBR,@–Rn 0100nnnn00010011 -STC.L VBR,@–Rn 0100nnnn00100011 -STS.L MACH,@–Rn 0100nnnn00000010 -STS.L MACL,@–Rn 0100nnnn00010010 -STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii */ @@ -601,8 +559,8 @@ TRAPA #imm 11000011iiiiiiii #define GET_Rn() \ ((op >> 8) & 0x0f) -#define CHECK_FX_GT_3() \ - if (GET_Fx() > 3) \ +#define CHECK_FX_LT(n) \ + if (GET_Fx() < n) \ goto default_ static void *sh2_translate(SH2 *sh2, block_desc *other_block) @@ -613,7 +571,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) int op, delayed_op = 0, test_irq = 0; int tcache_id = 0, blkid = 0; int cycles = 0; - u32 tmp, tmp2, tmp3; + u32 tmp, tmp2, tmp3, tmp4; // validate PC tmp = sh2->pc >> 29; @@ -673,6 +631,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) switch ((op >> 12) & 0x0f) { + ///////////////////////////////////////////// case 0x00: switch (op & 0x0f) { @@ -692,8 +651,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) default: goto default_; } - tmp2 = rcache_get_reg(tmp2, RC_GR_READ); - emith_move_r_r(tmp, tmp2); + tmp3 = rcache_get_reg(tmp2, RC_GR_READ); + emith_move_r_r(tmp, tmp3); + if (tmp2 == SHR_SR) + emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0 goto end_op; case 0x03: CHECK_UNHANDLED_BITS(0xd0); @@ -773,17 +734,18 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) switch (GET_Fx()) { case 0: // STS MACH,Rn 0000nnnn00001010 - tmp2 = rcache_get_reg(SHR_MACH, RC_GR_READ); + tmp2 = SHR_MACH; break; case 1: // STS MACL,Rn 0000nnnn00011010 - tmp2 = rcache_get_reg(SHR_MACL, RC_GR_READ); + tmp2 = SHR_MACL; break; case 2: // STS PR,Rn 0000nnnn00101010 - tmp2 = rcache_get_reg(SHR_PR, RC_GR_READ); + tmp2 = SHR_PR; break; default: goto default_; } + tmp2 = rcache_get_reg(tmp2, RC_GR_READ); emith_move_r_r(tmp, tmp2); goto end_op; case 0x0b: @@ -838,6 +800,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) } goto default_; + ///////////////////////////////////////////// case 0x01: // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd rcache_clean(); @@ -886,33 +849,347 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) emith_or_r_imm_c(DCOND_MI, tmp, T); EMITH_SJMP_END(DCOND_PL); goto end_op; + case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 + tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_bic_r_imm(tmp, T); + emith_tst_r_r(tmp2, tmp3); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp, T); + EMITH_SJMP_END(DCOND_NE); + goto end_op; + case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_and_r_r(tmp, tmp2); + goto end_op; + case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_eor_r_r(tmp, tmp2); + goto end_op; + case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_or_r_r(tmp, tmp2); + goto end_op; + case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100 + tmp = rcache_get_tmp(); + tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_eor_r_r_r(tmp, tmp2, tmp3); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(tmp2, T); + emith_tst_r_imm(tmp, 0x000000ff); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp2, T); + EMITH_SJMP_END(DCOND_NE); + emith_tst_r_imm(tmp, 0x0000ff00); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp2, T); + EMITH_SJMP_END(DCOND_NE); + emith_tst_r_imm(tmp, 0x00ff0000); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp2, T); + EMITH_SJMP_END(DCOND_NE); + emith_tst_r_imm(tmp, 0xff000000); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp2, T); + EMITH_SJMP_END(DCOND_NE); + rcache_free_tmp(tmp); + goto end_op; + case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_lsr(tmp, tmp, 16); + emith_or_r_r_r_lsl(tmp, tmp, tmp2, 16); + goto end_op; + case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110 + case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111 + tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); + if (op & 1) { + emith_sext(tmp, tmp2, 16); + } else + emith_clear_msb(tmp, tmp2, 16); + tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + tmp2 = rcache_get_tmp(); + if (op & 1) { + emith_sext(tmp2, tmp3, 16); + } else + emith_clear_msb(tmp2, tmp3, 16); + emith_mul(tmp, tmp, tmp2); + rcache_free_tmp(tmp2); +// FIXME: causes timing issues in Doom? +// cycles++; + goto end_op; } goto default_; + ///////////////////////////////////////////// + case 0x03: + switch (op & 0x0f) + { + case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000 + case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010 + case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 + case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 + case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 + tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + emith_bic_r_imm(tmp, T); + emith_cmp_r_r(tmp2, tmp3); + switch (op & 0x07) + { + case 0x00: // CMP/EQ + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp, T); + EMITH_SJMP_END(DCOND_NE); + break; + case 0x02: // CMP/HS + EMITH_SJMP_START(DCOND_LO); + emith_or_r_imm_c(DCOND_HS, tmp, T); + EMITH_SJMP_END(DCOND_LO); + break; + case 0x03: // CMP/GE + EMITH_SJMP_START(DCOND_LT); + emith_or_r_imm_c(DCOND_GE, tmp, T); + EMITH_SJMP_END(DCOND_LT); + break; + case 0x06: // CMP/HI + EMITH_SJMP_START(DCOND_LS); + emith_or_r_imm_c(DCOND_HI, tmp, T); + EMITH_SJMP_END(DCOND_LS); + break; + case 0x07: // CMP/GT + EMITH_SJMP_START(DCOND_LE); + emith_or_r_imm_c(DCOND_GT, tmp, T); + EMITH_SJMP_END(DCOND_LE); + break; + } + goto end_op; + case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100 + // TODO + break; + case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); + tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); + emith_mul_u64(tmp3, tmp4, tmp, tmp2); + goto end_op; + case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 + case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + if (op & 4) { + emith_add_r_r(tmp, tmp2); + } else + emith_sub_r_r(tmp, tmp2); + goto end_op; + case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010 + case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (op & 4) { // adc + emith_set_carry(tmp3); + emith_adcf_r_r(tmp, tmp2); + emith_carry_to_t(tmp3, 0); + } else { + emith_set_carry_sub(tmp3); + emith_sbcf_r_r(tmp, tmp2); + emith_carry_to_t(tmp3, 1); + } + goto end_op; + case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 + case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(tmp3, T); + if (op & 4) { + emith_addf_r_r(tmp, tmp2); + } else + emith_subf_r_r(tmp, tmp2); + EMITH_SJMP_START(DCOND_VC); + emith_or_r_imm_c(DCOND_VS, tmp3, T); + EMITH_SJMP_END(DCOND_VC); + goto end_op; + case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); + tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); + tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); + tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); + emith_mul_s64(tmp3, tmp4, tmp, tmp2); + goto end_op; + } + goto default_; + + ///////////////////////////////////////////// case 0x04: - switch (op & 0x0f) { + switch (op & 0x0f) + { case 0x00: - if ((op & 0xf0) != 0x10) - goto default_; - // DT Rn 0100nnnn00010000 - if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 - emith_sh2_dtbf_loop(); + switch (GET_Fx()) + { + case 0: // SHLL Rn 0100nnnn00000000 + case 2: // SHAL Rn 0100nnnn00100000 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_lslf(tmp, tmp, 1); + emith_carry_to_t(tmp2, 0); + goto end_op; + case 1: // DT Rn 0100nnnn00010000 + if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 + emith_sh2_dtbf_loop(); + goto end_op; + } + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(tmp2, T); + emith_subf_r_imm(tmp, 1); + EMITH_SJMP_START(DCOND_NE); + emith_or_r_imm_c(DCOND_EQ, tmp2, T); + EMITH_SJMP_END(DCOND_NE); goto end_op; } - tmp = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); - tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); - emith_bic_r_imm(tmp2, T); - emith_subf_r_imm(tmp, 1); - EMITH_SJMP_START(DCOND_NE); - emith_or_r_imm_c(DCOND_EQ, tmp2, T); - EMITH_SJMP_END(DCOND_NE); + goto default_; + case 0x01: + switch (GET_Fx()) + { + case 0: // SHLR Rn 0100nnnn00000001 + case 2: // SHAR Rn 0100nnnn00100001 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (op & 0x20) { + emith_asrf(tmp, tmp, 1); + } else + emith_lsrf(tmp, tmp, 1); + emith_carry_to_t(tmp2, 0); + goto end_op; + case 1: // CMP/PZ Rn 0100nnnn00010001 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(tmp2, T); + emith_cmp_r_imm(tmp, 0); + EMITH_SJMP_START(DCOND_LT); + emith_or_r_imm_c(DCOND_GE, tmp2, T); + EMITH_SJMP_END(DCOND_LT); + goto end_op; + } + goto default_; + case 0x02: + case 0x03: + switch (op & 0x3f) + { + case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010 + tmp = SHR_MACH; + break; + case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010 + tmp = SHR_MACL; + break; + case 0x22: // STS.L PR,@–Rn 0100nnnn00100010 + tmp = SHR_PR; + break; + case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 + tmp = SHR_SR; + break; + case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 + tmp = SHR_GBR; + break; + case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 + tmp = SHR_VBR; + break; + default: + goto default_; + } + tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); + emith_sub_r_imm(tmp2, 4); + rcache_clean(); + rcache_get_reg_arg(0, GET_Rn()); + tmp3 = rcache_get_reg_arg(1, tmp); + if (tmp == SHR_SR) + emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0 + emit_memhandler_write(2); goto end_op; + case 0x04: + case 0x05: + switch (op & 0x3f) + { + case 0x04: // ROTL Rn 0100nnnn00000100 + case 0x05: // ROTR Rn 0100nnnn00000101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (op & 1) { + emith_rorf(tmp, tmp, 1); + } else + emith_rolf(tmp, tmp, 1); + emith_carry_to_t(tmp2, 0); + goto end_op; + case 0x24: // ROTCL Rn 0100nnnn00100100 + case 0x25: // ROTCR Rn 0100nnnn00100101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_set_carry(tmp2); + if (op & 1) { + emith_rorcf(tmp); + } else + emith_rolcf(tmp); + emith_carry_to_t(tmp2, 0); + goto end_op; + case 0x15: // CMP/PL Rn 0100nnnn00010101 + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(tmp2, T); + emith_cmp_r_imm(tmp, 0); + EMITH_SJMP_START(DCOND_LE); + emith_or_r_imm_c(DCOND_GT, tmp2, T); + EMITH_SJMP_END(DCOND_LE); + goto end_op; + } + goto default_; + case 0x06: case 0x07: - if ((op & 0xf0) != 0) + switch (op & 0x3f) + { + case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110 + tmp = SHR_MACH; + break; + case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110 + tmp = SHR_MACL; + break; + case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110 + tmp = SHR_PR; + break; + case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 + tmp = SHR_SR; + break; + case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 + tmp = SHR_GBR; + break; + case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 + tmp = SHR_VBR; + break; + default: goto default_; - // LDC.L @Rm+,SR 0100mmmm00000111 - test_irq = 1; - goto default_; + } + rcache_clean(); + rcache_get_reg_arg(0, GET_Rn()); + tmp2 = emit_memhandler_read(2); + if (tmp == SHR_SR) { + emith_write_sr(tmp2); + test_irq = 1; + } else { + tmp = rcache_get_reg(tmp, RC_GR_WRITE); + emith_move_r_r(tmp, tmp2); + } + rcache_free_tmp(tmp2); + tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); + emith_add_r_imm(tmp, 4); + goto end_op; case 0x0b: if ((op & 0xd0) != 0) goto default_; @@ -933,6 +1210,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) } goto default_; + ///////////////////////////////////////////// case 0x08: switch (op & 0x0f00) { // BT/S label 10001101dddddddd @@ -968,6 +1246,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) }} goto default_; + ///////////////////////////////////////////// case 0x0a: // BRA label 1010dddddddddddd DELAYED_OP; @@ -977,6 +1256,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) cycles++; break; + ///////////////////////////////////////////// case 0x0b: // BSR label 1011dddddddddddd DELAYED_OP;