X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fsh2%2Fcompiler.c;h=c57c4b5a6e8d832a1f64234b2f96005931de1c72;hb=8cc76b48865096cff1024d1d7cfb4123bf7daba7;hp=2f959d2b89a1dd2b5b5bdf5bd95d926a60da6d6c;hpb=f4c0720c249d4d51f13f9cd69e3f149dcdf64a9e;p=picodrive.git diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index 2f959d2..c57c4b5 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -1,6 +1,6 @@ /* * SH2 recompiler - * (C) notaz, 2009,2010 + * (C) notaz, 2009,2010,2013 * * This work is licensed under the terms of MAME license. * See COPYING file in the top-level directory. @@ -8,10 +8,8 @@ * notes: * - tcache, block descriptor, link buffer overflows result in sh2_translate() * failure, followed by full tcache invalidation for that region - * - jumps between blocks are tracked for SMC handling (in block_links[]), + * - jumps between blocks are tracked for SMC handling (in block_entry->links), * except jumps between different tcaches - * - non-main block entries are called subblocks, as they have same tracking - * structures that main blocks have. * * implemented: * - static register allocation @@ -41,15 +39,28 @@ #define LINK_BRANCHES 1 // limits (per block) -#define BLOCK_CYCLE_LIMIT 100 -#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) +#define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6) // max literal offset from the block end #define MAX_LITERAL_OFFSET 32*2 -#define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4) +#define MAX_LITERALS (BLOCK_INSN_LIMIT / 4) #define MAX_LOCAL_BRANCHES 32 -// debug stuff { +/// +#define FETCH_OP(pc) \ + dr_pc_base[(pc) / 2] + +#define FETCH32(a) \ + ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1]) + +#ifdef DRC_SH2 + +// debug stuff +// 1 - warnings/errors +// 2 - block info/smc +// 4 - asm +// 8 - runtime block entry log +// { #ifndef DRC_DEBUG #define DRC_DEBUG 0 #endif @@ -100,7 +111,7 @@ static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr) // and can be discarded early // XXX: need to tune sizes static const int tcache_sizes[TCACHE_BUFFERS] = { - DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM + DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 DRC_TCACHE_SIZE / 8, // ... slave }; @@ -111,30 +122,78 @@ static u8 *tcache_ptrs[TCACHE_BUFFERS]; // ptr for code emiters static u8 *tcache_ptr; -typedef struct block_desc_ { - u32 addr; // SH2 PC address +#define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8) + +struct block_link { + u32 target_pc; + void *jump; // insn address + struct block_link *next; // either in block_entry->links or +}; + +struct block_entry { + u32 pc; void *tcache_ptr; // translated block for above PC - struct block_desc_ *next; // next block with the same PC hash + struct block_entry *next; // next block in hash_table with same pc hash + struct block_link *links; // links to this entry #if (DRC_DEBUG & 2) - int refcount; + struct block_desc *block; #endif -} block_desc; +}; -typedef struct block_link_ { - u32 target_pc; - void *jump; // insn address -// struct block_link_ *next; -} block_link; +struct block_desc { + u32 addr; // block start SH2 PC address + u32 end_addr; // address after last op or literal +#if (DRC_DEBUG & 2) + int refcount; +#endif + int entry_count; + struct block_entry entryp[MAX_BLOCK_ENTRIES]; +}; static const int block_max_counts[TCACHE_BUFFERS] = { 4*1024, 256, 256, }; -static block_desc *block_tables[TCACHE_BUFFERS]; -static block_link *block_links[TCACHE_BUFFERS]; +static struct block_desc *block_tables[TCACHE_BUFFERS]; static int block_counts[TCACHE_BUFFERS]; -static int block_link_counts[TCACHE_BUFFERS]; + +// we have block_link_pool to avoid using mallocs +static const int block_link_pool_max_counts[TCACHE_BUFFERS] = { + 4*1024, + 256, + 256, +}; +static struct block_link *block_link_pool[TCACHE_BUFFERS]; +static int block_link_pool_counts[TCACHE_BUFFERS]; +static struct block_link *unresolved_links[TCACHE_BUFFERS]; + +// used for invalidation +static const int ram_sizes[TCACHE_BUFFERS] = { + 0x40000, + 0x1000, + 0x1000, +}; +#define ADDR_TO_BLOCK_PAGE 0x100 + +struct block_list { + struct block_desc *block; + struct block_list *next; +}; + +// array of pointers to block_lists for RAM and 2 data arrays +// each array has len: sizeof(mem) / ADDR_TO_BLOCK_PAGE +static struct block_list **inval_lookup[TCACHE_BUFFERS]; + +static const int hash_table_sizes[TCACHE_BUFFERS] = { + 0x1000, + 0x100, + 0x100, +}; +static struct block_entry **hash_tables[TCACHE_BUFFERS]; + +#define HASH_FUNC(hash_tab, addr, mask) \ + (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)] // host register tracking enum { @@ -215,14 +274,6 @@ static temp_reg_t reg_temp[] = { #define Q_SHIFT 8 #define M_SHIFT 9 -// ROM hash table -#define MAX_HASH_ENTRIES 1024 -#define HASH_MASK (MAX_HASH_ENTRIES - 1) -static void **hash_table; - -#define HASH_FUNC(hash_tab, addr) \ - ((block_desc **)(hash_tab))[(addr) & HASH_MASK] - static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2); static void (*sh2_drc_dispatcher)(void); static void (*sh2_drc_exit)(void); @@ -232,46 +283,10 @@ static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2); static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2); static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2); static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d); -static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d); static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); -static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d); static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2); -extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); - // address space stuff -static void *dr_get_pc_base(u32 pc, int is_slave) -{ - void *ret = NULL; - u32 mask = 0; - - if ((pc & ~0x7ff) == 0) { - // BIOS - ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; - mask = 0x7ff; - } - else if ((pc & 0xfffff000) == 0xc0000000) { - // data array - ret = Pico32xMem->data_array[is_slave]; - mask = 0xfff; - } - else if ((pc & 0xc6000000) == 0x06000000) { - // SDRAM - ret = Pico32xMem->sdram; - mask = 0x03ffff; - } - else if ((pc & 0xc6000000) == 0x02000000) { - // ROM - ret = Pico.rom; - mask = 0x3fffff; - } - - if (ret == NULL) - return (void *)-1; // NULL is valid value - - return (char *)ret - (pc & ~mask); -} - static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) { int poffs = -1; @@ -300,32 +315,22 @@ static int dr_ctx_get_mem_ptr(u32 a, u32 *mask) return poffs; } -static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id) +static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id) { - *tcache_id = 0; - - // we have full block id tables for data_array and RAM - // BIOS goes to data_array table too - if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) { - int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; - *tcache_id = 1 + is_slave; - if (blkid & 1) - return &block_tables[*tcache_id][blkid >> 1]; - } - // RAM - else if ((pc & 0xc6000000) == 0x06000000) { - int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; - if (blkid & 1) - return &block_tables[0][blkid >> 1]; - } - // ROM - else if ((pc & 0xc6000000) == 0x02000000) { - block_desc *bd = HASH_FUNC(hash_table, pc); + struct block_entry *be; + u32 tcid = 0, mask; - for (; bd != NULL; bd = bd->next) - if (bd->addr == pc) - return bd; - } + // data arrays have their own caches + if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) + tcid = 1 + is_slave; + + *tcache_id = tcid; + + mask = hash_table_sizes[tcid] - 1; + be = HASH_FUNC(hash_tables[tcid], pc, mask); + for (; be != NULL; be = be->next) + if (be->pc == pc) + return be; return NULL; } @@ -333,100 +338,166 @@ static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id) // --------------------------------------------------------------- // block management +static void add_to_block_list(struct block_list **blist, struct block_desc *block) +{ + struct block_list *added = malloc(sizeof(*added)); + if (!added) { + elprintf(EL_ANOMALY, "drc OOM (1)"); + return; + } + added->block = block; + added->next = *blist; + *blist = added; +} + +static void rm_from_block_list(struct block_list **blist, struct block_desc *block) +{ + struct block_list *prev = NULL, *current = *blist; + for (; current != NULL; prev = current, current = current->next) { + if (current->block == block) { + if (prev == NULL) + *blist = current->next; + else + prev->next = current->next; + free(current); + return; + } + } + dbg(1, "can't rm block %p (%08x-%08x)", + block, block->addr, block->end_addr); +} + +static void rm_block_list(struct block_list **blist) +{ + struct block_list *tmp, *current = *blist; + while (current != NULL) { + tmp = current; + current = current->next; + free(tmp); + } + *blist = NULL; +} + static void REGPARM(1) flush_tcache(int tcid) { + int i; + dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid, tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], block_counts[tcid], block_max_counts[tcid]); block_counts[tcid] = 0; - block_link_counts[tcid] = 0; + block_link_pool_counts[tcid] = 0; + unresolved_links[tcid] = NULL; + memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]); tcache_ptrs[tcid] = tcache_bases[tcid]; - if (tcid == 0) { // ROM, RAM - memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); - memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); + if (Pico32xMem != NULL) { + if (tcid == 0) // ROM, RAM + memset(Pico32xMem->drcblk_ram, 0, + sizeof(Pico32xMem->drcblk_ram)); + else + memset(Pico32xMem->drcblk_da[tcid - 1], 0, + sizeof(Pico32xMem->drcblk_da[0])); } - else - memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); #if (DRC_DEBUG & 4) tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; #endif + + for (i = 0; i < ram_sizes[tcid] / ADDR_TO_BLOCK_PAGE; i++) + rm_block_list(&inval_lookup[tcid][i]); } -#if LINK_BRANCHES -// add block links (tracked branches) -static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id) +static void add_to_hashlist(struct block_entry *be, int tcache_id) { - block_link *bl = block_links[tcache_id]; - int cnt = block_link_counts[tcache_id]; + u32 tcmask = hash_table_sizes[tcache_id] - 1; - if (cnt >= block_max_counts[tcache_id] * 2) { - dbg(1, "bl overflow for tcache %d\n", tcache_id); - return -1; + be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask); + HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be; + +#if (DRC_DEBUG & 2) + if (be->next != NULL) { + printf(" %08x: hash collision with %08x\n", + be->pc, be->next->pc); + hash_collisions++; } +#endif +} - bl[cnt].target_pc = target_pc; - bl[cnt].jump = jump; - block_link_counts[tcache_id]++; +static void rm_from_hashlist(struct block_entry *be, int tcache_id) +{ + u32 tcmask = hash_table_sizes[tcache_id] - 1; + struct block_entry *cur, *prev; + + cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask); + if (cur == NULL) + goto missing; + + if (be == cur) { // first + HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next; + return; + } - return 0; + for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) { + if (cur == be) { + prev->next = cur->next; + return; + } + } + +missing: + dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc); } -#endif -static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id) +static struct block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id) { - block_desc *bd; + struct block_entry *be; + struct block_desc *bd; int tcache_id; int *bcount; - bd = dr_get_bd(addr, is_slave, &tcache_id); - if (bd != NULL) { - dbg(2, "block override for %08x", addr); - bd->tcache_ptr = tcache_ptr; - *blk_id = bd - block_tables[tcache_id]; - return bd; - } + // do a lookup to get tcache_id and override check + be = dr_get_entry(addr, is_slave, &tcache_id); + if (be != NULL) + dbg(1, "block override for %08x", addr); bcount = &block_counts[tcache_id]; if (*bcount >= block_max_counts[tcache_id]) { dbg(1, "bd overflow for tcache %d", tcache_id); return NULL; } - if (*bcount == 0) - (*bcount)++; // not using descriptor 0 bd = &block_tables[tcache_id][*bcount]; bd->addr = addr; - bd->tcache_ptr = tcache_ptr; - *blk_id = *bcount; - (*bcount)++; + bd->end_addr = end_addr; - if ((addr & 0xc6000000) == 0x02000000) { // ROM - bd->next = HASH_FUNC(hash_table, addr); - HASH_FUNC(hash_table, addr) = bd; + bd->entry_count = 1; + bd->entryp[0].pc = addr; + bd->entryp[0].tcache_ptr = tcache_ptr; + bd->entryp[0].links = NULL; #if (DRC_DEBUG & 2) - if (bd->next != NULL) { - printf(" hash collision with %08x\n", bd->next->addr); - hash_collisions++; - } + bd->entryp[0].block = bd; + bd->refcount = 0; #endif - } + add_to_hashlist(&bd->entryp[0], tcache_id); + + *blk_id = *bcount; + (*bcount)++; return bd; } static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id) { - block_desc *bd = NULL; + struct block_entry *be = NULL; void *block = NULL; - bd = dr_get_bd(pc, is_slave, tcache_id); - if (bd != NULL) - block = bd->tcache_ptr; + be = dr_get_entry(pc, is_slave, tcache_id); + if (be != NULL) + block = be->tcache_ptr; #if (DRC_DEBUG & 2) - if (bd != NULL) - bd->refcount++; + if (be != NULL) + be->block->refcount++; #endif return block; } @@ -437,43 +508,79 @@ static void *dr_failure(void) exit(1); } -static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id) +static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id) { #if LINK_BRANCHES + struct block_link *bl = block_link_pool[tcache_id]; + int cnt = block_link_pool_counts[tcache_id]; + struct block_entry *be = NULL; int target_tcache_id; - void *target; - int ret; - - target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id); - if (target_tcache_id == tcache_id) { - // allow linking blocks only from local cache - ret = dr_add_block_link(pc, tcache_ptr, tcache_id); - if (ret < 0) - return NULL; + int i; + + be = dr_get_entry(pc, is_slave, &target_tcache_id); + if (target_tcache_id != tcache_id) + return sh2_drc_dispatcher; + + // if pool has been freed, reuse + for (i = cnt - 1; i >= 0; i--) + if (bl[i].target_pc != 0) + break; + cnt = i + 1; + if (cnt >= block_link_pool_max_counts[tcache_id]) { + dbg(1, "bl overflow for tcache %d\n", tcache_id); + return NULL; } - if (target == NULL || target_tcache_id != tcache_id) - target = sh2_drc_dispatcher; + bl += cnt; + block_link_pool_counts[tcache_id]++; + + bl->target_pc = pc; + bl->jump = tcache_ptr; - return target; + if (be != NULL) { + dbg(2, "- early link from %p to pc %08x", bl->jump, pc); + bl->next = be->links; + be->links = bl; + return be->tcache_ptr; + } + else { + bl->next = unresolved_links[tcache_id]; + unresolved_links[tcache_id] = bl; + return sh2_drc_dispatcher; + } #else return sh2_drc_dispatcher; #endif } -static void dr_link_blocks(void *target, u32 pc, int tcache_id) +static void dr_link_blocks(struct block_entry *be, int tcache_id) { #if LINK_BRANCHES - block_link *bl = block_links[tcache_id]; - int cnt = block_link_counts[tcache_id]; - int i; - - for (i = 0; i < cnt; i++) { - if (bl[i].target_pc == pc) { - dbg(2, "- link from %p", bl[i].jump); - emith_jump_patch(bl[i].jump, target); - // XXX: sync ARM caches (old jump should be fine)? + struct block_link *first = unresolved_links[tcache_id]; + struct block_link *bl, *prev, *tmp; + u32 pc = be->pc; + + for (bl = prev = first; bl != NULL; ) { + if (bl->target_pc == pc) { + dbg(2, "- link from %p to pc %08x", bl->jump, pc); + emith_jump_patch(bl->jump, tcache_ptr); + + // move bl from unresolved_links to block_entry + tmp = bl->next; + bl->next = be->links; + be->links = bl; + + if (bl == first) + first = prev = bl = tmp; + else + prev->next = bl = tmp; + continue; } + prev = bl; + bl = bl->next; } + unresolved_links[tcache_id] = first; + + // could sync arm caches here, but that's unnecessary #endif } @@ -1040,7 +1147,7 @@ static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int siz return hr2; } -static void emit_memhandler_write(int size, u32 pc, int delay) +static void emit_memhandler_write(int size, u32 pc) { int ctxr; host_arg2reg(ctxr, 2); @@ -1050,22 +1157,12 @@ static void emit_memhandler_write(int size, u32 pc, int delay) switch (size) { case 0: // 8 // XXX: consider inlining sh2_drc_write8 - if (delay) { - emith_call(sh2_drc_write8_slot); - } else { - emit_move_r_imm32(SHR_PC, pc); - rcache_clean(); - emith_call(sh2_drc_write8); - } + rcache_clean(); + emith_call(sh2_drc_write8); break; case 1: // 16 - if (delay) { - emith_call(sh2_drc_write16_slot); - } else { - emit_move_r_imm32(SHR_PC, pc); - rcache_clean(); - emith_call(sh2_drc_write16); - } + rcache_clean(); + emith_call(sh2_drc_write16); break; case 2: // 32 emith_move_r_r(ctxr, CONTEXT_REG); @@ -1073,9 +1170,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay) break; } + rcache_invalidate(); if (reg_map_g2h[SHR_SR] != -1) emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4); - rcache_invalidate(); } // @(Rx,Ry) @@ -1186,12 +1283,6 @@ static void emit_block_entry(void) goto default_; \ } -#define FETCH_OP(pc) \ - dr_pc_base[(pc) / 2] - -#define FETCH32(a) \ - ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1]) - #define GET_Fx() \ ((op >> 4) & 0x0f) @@ -1204,16 +1295,13 @@ static void emit_block_entry(void) if (GET_Fx() >= n) \ goto default_ -// op_flags: data from 1st pass -#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2] -#define OF_DELAY_OP (1 << 0) +static void *dr_get_pc_base(u32 pc, int is_slave); static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) { // XXX: maybe use structs instead? u32 branch_target_pc[MAX_LOCAL_BRANCHES]; void *branch_target_ptr[MAX_LOCAL_BRANCHES]; - int branch_target_blkid[MAX_LOCAL_BRANCHES]; int branch_target_count = 0; void *branch_patch_ptr[MAX_LOCAL_BRANCHES]; u32 branch_patch_pc[MAX_LOCAL_BRANCHES]; @@ -1222,7 +1310,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) int literal_addr_count = 0; int pending_branch_cond = -1; int pending_branch_pc = 0; - u8 op_flags[BLOCK_CYCLE_LIMIT + 1]; + u8 op_flags[BLOCK_INSN_LIMIT]; struct { u32 delayed_op:2; u32 test_irq:1; @@ -1231,15 +1319,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) // PC of current, first, last, last_target_blk SH2 insn u32 pc, base_pc, end_pc, out_pc; - void *block_entry; - block_desc *this_block; + void *block_entry_ptr; + struct block_desc *block; u16 *dr_pc_base; int blkid_main = 0; int skip_op = 0; u32 tmp, tmp2; int cycles; + int i, v; int op; - int i; base_pc = sh2->pc; @@ -1252,9 +1340,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) } tcache_ptr = tcache_ptrs[tcache_id]; - this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main); - if (this_block == NULL) - return NULL; // predict tcache overflow tmp = tcache_ptr - tcache_bases[tcache_id]; @@ -1263,66 +1348,33 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) return NULL; } - block_entry = tcache_ptr; - dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', - tcache_id, blkid_main, base_pc, block_entry); - - dr_link_blocks(tcache_ptr, base_pc, tcache_id); - // 1st pass: scan forward for local branches - memset(op_flags, 0, sizeof(op_flags)); - for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) { - op = FETCH_OP(pc); - if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR - signed int offs = ((signed int)(op << 20) >> 19); - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,); - break; - } - if ((op & 0xf000) == 0) { - op &= 0xff; - if (op == 0x1b) // SLEEP - break; - if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - break; - } - continue; - } - if ((op & 0xf0df) == 0x400b) { // JMP, JSR - pc += 2; - OP_FLAGS(pc) |= OF_DELAY_OP; - break; - } - if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) - signed int offs = ((signed int)(op << 24) >> 23); - if (op & 0x0400) - OP_FLAGS(pc + 2) |= OF_DELAY_OP; - ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break); - } - if ((op & 0xff00) == 0xc300) // TRAPA - break; - } + scan_block(base_pc, sh2->is_slave, op_flags, &end_pc); - end_pc = pc; + block = dr_add_block(base_pc, end_pc + MAX_LITERAL_OFFSET, // XXX + sh2->is_slave, &blkid_main); + if (block == NULL) + return NULL; - // clean branch_targets that are not really local, - // and that land on delay slots - for (i = 0, tmp = 0; i < branch_target_count; i++) { - pc = branch_target_pc[i]; - if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP)) - branch_target_pc[tmp++] = branch_target_pc[i]; + block_entry_ptr = tcache_ptr; + dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm', + tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr); - if (i == branch_target_count - 1) // workaround gcc 4.5.2 bug? - break; + dr_link_blocks(&block->entryp[0], tcache_id); + + // collect branch_targets that don't land on delay slots + for (pc = base_pc; pc < end_pc; pc += 2) { + if (!(OP_FLAGS(pc) & OF_BTARGET)) + continue; + if (OP_FLAGS(pc) & OF_DELAY_OP) { + OP_FLAGS(pc) &= ~OF_BTARGET; + continue; + } + ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break); } - branch_target_count = tmp; if (branch_target_count > 0) { memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); - memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count); } // ------------------------------------------------- @@ -1338,13 +1390,12 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) op = FETCH_OP(pc); - i = find_in_array(branch_target_pc, branch_target_count, pc); - if (i >= 0 || pc == base_pc) + if ((OP_FLAGS(pc) & OF_BTARGET) || pc == base_pc) { + i = find_in_array(branch_target_pc, branch_target_count, pc); if (pc != base_pc) { - /* make "subblock" - just a mid-block entry */ - block_desc *subblock; + // make block entry sr = rcache_get_reg(SHR_SR, RC_GR_RMW); FLUSH_CYCLES(sr); @@ -1355,15 +1406,28 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_flush(); do_host_disasm(tcache_id); - dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', - tcache_id, branch_target_blkid[i], pc, tcache_ptr); + v = block->entry_count; + if (v < ARRAY_SIZE(block->entryp)) { + block->entryp[v].pc = pc; + block->entryp[v].tcache_ptr = tcache_ptr; + block->entryp[v].links = NULL; +#if (DRC_DEBUG & 2) + block->entryp[v].block = block; +#endif + add_to_hashlist(&block->entryp[v], tcache_id); + block->entry_count++; - subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]); - if (subblock == NULL) - return NULL; + dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p", sh2->is_slave ? 's' : 'm', + tcache_id, blkid_main, pc, tcache_ptr); - // since we made a block entry, link any other blocks that jump to current pc - dr_link_blocks(tcache_ptr, pc, tcache_id); + // since we made a block entry, link any other blocks + // that jump to current pc + dr_link_blocks(&block->entryp[v], tcache_id); + } + else { + dbg(1, "too many entryp for block #%d,%d pc=%08x", + tcache_id, blkid_main, pc); + } } if (i >= 0) branch_target_ptr[i] = tcache_ptr; @@ -1382,10 +1446,26 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) #if (DRC_DEBUG & 2) insns_compiled++; +#endif #if (DRC_DEBUG & 4) DasmSH2(sh2dasm_buff, pc, op); - printf("%08x %04x %s\n", pc, op, sh2dasm_buff); + printf("%c%08x %04x %s\n", (OP_FLAGS(pc) & OF_BTARGET) ? '*' : ' ', + pc, op, sh2dasm_buff); #endif +#ifdef DRC_CMP + //if (out_pc != 0 && out_pc != (u32)-1) + // emit_move_r_imm32(SHR_PC, out_pc); + //else + if (!drcf.delayed_op) { + emit_move_r_imm32(SHR_PC, pc); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + FLUSH_CYCLES(sr); + // rcache_clean(); // FIXME + rcache_flush(); + emit_do_static_regs(1, 0); + emith_pass_arg_r(0, CONTEXT_REG); + emith_call(do_sh2_cmp); + } #endif pc += 2; @@ -1449,7 +1529,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(0, SHR_R0); tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ); emith_add_r_r(tmp2, tmp3); - emit_memhandler_write(op & 3, pc, drcf.delayed_op); + emit_memhandler_write(op & 3, pc); goto end_op; case 0x07: // MUL.L Rm,Rn 0000nnnnmmmm0111 @@ -1603,7 +1683,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) EMITH_JMP_END(DCOND_EQ); rcache_free_tmp(tmp); - cycles += 3; + cycles += 2; goto end_op; } goto default_; @@ -1616,7 +1696,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(1, GET_Rm()); if (op & 0x0f) emith_add_r_imm(tmp, (op & 0x0f) * 4); - emit_memhandler_write(2, pc, drcf.delayed_op); + emit_memhandler_write(2, pc); goto end_op; case 0x02: @@ -1628,7 +1708,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(1, GET_Rm()); - emit_memhandler_write(op & 3, pc, drcf.delayed_op); + emit_memhandler_write(op & 3, pc); goto end_op; case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 @@ -1638,7 +1718,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(1, GET_Rm()); - emit_memhandler_write(op & 3, pc, drcf.delayed_op); + emit_memhandler_write(op & 3, pc); goto end_op; case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); @@ -1726,8 +1806,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_clear_msb(tmp2, tmp3, 16); emith_mul(tmp, tmp, tmp2); rcache_free_tmp(tmp2); -// FIXME: causes timing issues in Doom? -// cycles++; goto end_op; } goto default_; @@ -1815,6 +1893,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); emith_mul_u64(tmp3, tmp4, tmp, tmp2); + cycles++; goto end_op; case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100 @@ -1864,6 +1943,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE); emith_mul_s64(tmp3, tmp4, tmp, tmp2); + cycles++; goto end_op; } goto default_; @@ -1889,6 +1969,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) sr = rcache_get_reg(SHR_SR, RC_GR_RMW); if (drcf.delayed_op) DELAY_SAVE_T(sr); +#ifndef DRC_CMP if (FETCH_OP(pc) == 0x8bfd) { // BF #-2 if (gconst_get(GET_Rn(), &tmp)) { // XXX: limit burned cycles @@ -1901,6 +1982,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_sh2_dtbf_loop(); goto end_op; } +#endif tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); emith_bic_r_imm(sr, T); emith_subf_r_imm(tmp, 1); @@ -1952,12 +2034,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) break; case 0x03: // STC.L SR,@–Rn 0100nnnn00000011 tmp = SHR_SR; + cycles++; break; case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011 tmp = SHR_GBR; + cycles++; break; case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011 tmp = SHR_VBR; + cycles++; break; default: goto default_; @@ -1969,7 +2054,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg_arg(1, tmp); if (tmp == SHR_SR) emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0 - emit_memhandler_write(2, pc, drcf.delayed_op); + emit_memhandler_write(2, pc); goto end_op; case 0x04: case 0x05: @@ -2029,12 +2114,15 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) break; case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111 tmp = SHR_SR; + cycles += 2; break; case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111 tmp = SHR_GBR; + cycles += 2; break; case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111 tmp = SHR_VBR; + cycles += 2; break; default: goto default_; @@ -2128,8 +2216,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_move_r_r(tmp2, tmp); rcache_free_tmp(tmp); rcache_get_reg_arg(0, GET_Rn()); - emit_memhandler_write(0, pc, drcf.delayed_op); - cycles += 3; + emit_memhandler_write(0, pc); break; default: goto default_; @@ -2294,7 +2381,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = (op & 0x100) >> 8; if (op & 0x0f) emith_add_r_imm(tmp, (op & 0x0f) << tmp3); - emit_memhandler_write(tmp3, pc, drcf.delayed_op); + emit_memhandler_write(tmp3, pc); goto end_op; case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd @@ -2317,7 +2404,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) case 0x0d00: // BT/S label 10001101dddddddd case 0x0f00: // BF/S label 10001111dddddddd DELAYED_OP; - cycles--; // fallthrough case 0x0900: // BT label 10001001dddddddd case 0x0b00: // BF label 10001011dddddddd @@ -2325,7 +2411,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; i = ((signed int)(op << 24) >> 23); pending_branch_pc = pc + i + 2; - cycles += 2; goto end_op; } goto default_; @@ -2385,7 +2470,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp2 = rcache_get_reg_arg(1, SHR_R0); tmp3 = (op & 0x300) >> 8; emith_add_r_imm(tmp, (op & 0xff) << tmp3); - emit_memhandler_write(tmp3, pc, drcf.delayed_op); + emit_memhandler_write(tmp3, pc); goto end_op; case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd @@ -2401,12 +2486,12 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) emith_add_r_imm(tmp, 4); tmp = rcache_get_reg_arg(1, SHR_SR); emith_clear_msb(tmp, tmp, 22); - emit_memhandler_write(2, pc, drcf.delayed_op); + emit_memhandler_write(2, pc); // push PC rcache_get_reg_arg(0, SHR_SP); tmp = rcache_get_tmp_arg(1); emith_move_r_imm(tmp, pc); - emit_memhandler_write(2, pc, drcf.delayed_op); + emit_memhandler_write(2, pc); // obtain new PC emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2); out_pc = (u32)-1; @@ -2465,8 +2550,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) tmp3 = rcache_get_reg_arg(0, SHR_GBR); tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ); emith_add_r_r(tmp3, tmp4); - emit_memhandler_write(0, pc, drcf.delayed_op); - cycles += 2; + emit_memhandler_write(0, pc); goto end_op; } goto default_; @@ -2502,13 +2586,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) default_: elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x", sh2->is_slave ? 's' : 'm', op, pc - 2); -#ifdef DRC_DEBUG_INTERP - emit_move_r_imm32(SHR_PC, pc - 2); - rcache_flush(); - emith_pass_arg_r(0, CONTEXT_REG); - emith_pass_arg_imm(1, op); - emith_call(sh2_do_op); -#endif break; } @@ -2519,17 +2596,20 @@ end_op: if (pending_branch_cond != -1 && drcf.delayed_op != 2) { u32 target_pc = pending_branch_pc; + int ctaken = drcf.delayed_op ? 1 : 2; void *target; sr = rcache_get_reg(SHR_SR, RC_GR_RMW); - // handle cycles FLUSH_CYCLES(sr); - rcache_clean(); if (drcf.use_saved_t) emith_tst_r_imm(sr, T_save); else emith_tst_r_imm(sr, T); + // handle cycles + emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12); + rcache_clean(); + #if LINK_BRANCHES if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) { // local branch @@ -2551,7 +2631,7 @@ end_op: emit_move_r_imm32(SHR_PC, target_pc); rcache_clean(); - target = dr_prepare_ext_branch(target_pc, sh2, tcache_id); + target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id); if (target == NULL) return NULL; emith_jump_cond_patchable(pending_branch_cond, target); @@ -2593,7 +2673,7 @@ end_op: emit_move_r_imm32(SHR_PC, out_pc); rcache_flush(); - target = dr_prepare_ext_branch(out_pc, sh2, tcache_id); + target = dr_prepare_ext_branch(out_pc, sh2->is_slave, tcache_id); if (target == NULL) return NULL; emith_jump_patchable(target); @@ -2620,10 +2700,10 @@ end_op: // mark memory blocks as containing compiled code // override any overlay blocks as they become unreachable anyway - if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000) + if (tcache_id != 0 || (block->addr & 0xc7fc0000) == 0x06000000) { u16 *drc_ram_blk = NULL; - u32 mask = 0, shift = 0; + u32 addr, mask = 0, shift = 0; if (tcache_id != 0) { // data array, BIOS @@ -2631,46 +2711,46 @@ end_op: shift = SH2_DRCBLK_DA_SHIFT; mask = 0xfff; } - else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { + else if ((block->addr & 0xc7fc0000) == 0x06000000) { // SDRAM drc_ram_blk = Pico32xMem->drcblk_ram; shift = SH2_DRCBLK_RAM_SHIFT; mask = 0x3ffff; } - drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1; - for (pc = base_pc + 2; pc < end_pc; pc += 2) - drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1; - - // mark subblocks - for (i = 0; i < branch_target_count; i++) - if (branch_target_blkid[i] != 0) - drc_ram_blk[(branch_target_pc[i] >> shift) & mask] = - (branch_target_blkid[i] << 1) | 1; + // mark recompiled insns + drc_ram_blk[(base_pc & mask) >> shift] = 1; + for (pc = base_pc; pc < end_pc; pc += 2) + drc_ram_blk[(pc & mask) >> shift] = 1; // mark literals for (i = 0; i < literal_addr_count; i++) { tmp = literal_addr[i]; - drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1; - if (!(tmp & 3)) // assume long - drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1; + drc_ram_blk[(tmp & mask) >> shift] = 1; + } + + // add to invalidation lookup lists + addr = base_pc & ~(ADDR_TO_BLOCK_PAGE - 1); + for (; addr < end_pc + MAX_LITERAL_OFFSET; addr += ADDR_TO_BLOCK_PAGE) { + i = (addr & mask) / ADDR_TO_BLOCK_PAGE; + add_to_block_list(&inval_lookup[tcache_id][i], block); } } tcache_ptrs[tcache_id] = tcache_ptr; - host_instructions_updated(block_entry, tcache_ptr); + host_instructions_updated(block_entry_ptr, tcache_ptr); do_host_disasm(tcache_id); dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", - tcache_id, block_counts[tcache_id], + tcache_id, blkid_main, tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], - insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); + insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled); if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); /* printf("~~~\n"); - tcache_dsm_ptrs[tcache_id] = block_entry; + tcache_dsm_ptrs[tcache_id] = block_entry_ptr; do_host_disasm(tcache_id); printf("~~~\n"); */ @@ -2679,13 +2759,12 @@ end_op: fflush(stdout); #endif - return block_entry; + return block_entry_ptr; } static void sh2_generate_utils(void) { int arg0, arg1, arg2, sr, tmp; - void *sh2_drc_write_end, *sh2_drc_write_slot_end; sh2_drc_write32 = p32x_sh2_write32; sh2_drc_read8 = p32x_sh2_read8; @@ -2786,51 +2865,15 @@ static void sh2_generate_utils(void) emith_call(sh2_drc_test_irq); emith_jump(sh2_drc_dispatcher); - // write-caused irq detection - sh2_drc_write_end = tcache_ptr; - emith_tst_r_r(arg0, arg0); - EMITH_SJMP_START(DCOND_NE); - emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return - EMITH_SJMP_END(DCOND_NE); - emith_call(sh2_drc_test_irq); - emith_jump_ctx(offsetof(SH2, drc_tmp)); - - // write-caused irq detection for writes in delay slot - sh2_drc_write_slot_end = tcache_ptr; - emith_tst_r_r(arg0, arg0); - EMITH_SJMP_START(DCOND_NE); - emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); - EMITH_SJMP_END(DCOND_NE); - // just burn cycles to get back to dispatcher after branch is handled - sr = rcache_get_reg(SHR_SR, RC_GR_RMW); - emith_ctx_write(sr, offsetof(SH2, irq_cycles)); - emith_clear_msb(sr, sr, 20); // clear cycles - rcache_flush(); - emith_jump_ctx(offsetof(SH2, drc_tmp)); - // sh2_drc_write8(u32 a, u32 d) sh2_drc_write8 = (void *)tcache_ptr; - emith_ret_to_ctx(offsetof(SH2, drc_tmp)); emith_ctx_read(arg2, offsetof(SH2, write8_tab)); - emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); + emith_sh2_wcall(arg0, arg2); // sh2_drc_write16(u32 a, u32 d) sh2_drc_write16 = (void *)tcache_ptr; - emith_ret_to_ctx(offsetof(SH2, drc_tmp)); - emith_ctx_read(arg2, offsetof(SH2, write16_tab)); - emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); - - // sh2_drc_write8_slot(u32 a, u32 d) - sh2_drc_write8_slot = (void *)tcache_ptr; - emith_ret_to_ctx(offsetof(SH2, drc_tmp)); - emith_ctx_read(arg2, offsetof(SH2, write8_tab)); - emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); - - // sh2_drc_write16_slot(u32 a, u32 d) - sh2_drc_write16_slot = (void *)tcache_ptr; - emith_ret_to_ctx(offsetof(SH2, drc_tmp)); emith_ctx_read(arg2, offsetof(SH2, write16_tab)); - emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); + emith_sh2_wcall(arg0, arg2); #ifdef PDB_NET // debug @@ -2864,9 +2907,7 @@ static void sh2_generate_utils(void) MAKE_READ_WRAPPER(sh2_drc_read16); MAKE_READ_WRAPPER(sh2_drc_read32); MAKE_WRITE_WRAPPER(sh2_drc_write8); - MAKE_WRITE_WRAPPER(sh2_drc_write8_slot); MAKE_WRITE_WRAPPER(sh2_drc_write16); - MAKE_WRITE_WRAPPER(sh2_drc_write16_slot); MAKE_WRITE_WRAPPER(sh2_drc_write32); #if (DRC_DEBUG & 4) host_dasm_new_symbol(sh2_drc_read8); @@ -2882,97 +2923,93 @@ static void sh2_generate_utils(void) host_dasm_new_symbol(sh2_drc_dispatcher); host_dasm_new_symbol(sh2_drc_exit); host_dasm_new_symbol(sh2_drc_test_irq); - host_dasm_new_symbol(sh2_drc_write_end); - host_dasm_new_symbol(sh2_drc_write_slot_end); host_dasm_new_symbol(sh2_drc_write8); - host_dasm_new_symbol(sh2_drc_write8_slot); host_dasm_new_symbol(sh2_drc_write16); - host_dasm_new_symbol(sh2_drc_write16_slot); #endif } -static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id) +static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask) { + struct block_link *bl, *bl_next, *bl_unresolved; void *tmp; + u32 i, addr; - // XXX: kill links somehow? - dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]); - if (bd->addr == 0 || bd->tcache_ptr == NULL) { + dbg(2, " killing entry %08x-%08x, blkid %d,%d", + bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]); + if (bd->addr == 0 || bd->entry_count == 0) { dbg(1, " killing dead block!? %08x", bd->addr); - return bd->tcache_ptr; + return; } - // since we never reuse space of dead blocks, - // insert jump to dispatcher for blocks that are linked to this point - //emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher); + // remove from inval_lookup + addr = bd->addr & ~(ADDR_TO_BLOCK_PAGE - 1); + for (; addr < bd->end_addr; addr += ADDR_TO_BLOCK_PAGE) { + i = (addr & ram_mask) / ADDR_TO_BLOCK_PAGE; + rm_from_block_list(&inval_lookup[tcache_id][i], bd); + } - // attempt to handle self-modifying blocks by exiting at nearest known PC tmp = tcache_ptr; - tcache_ptr = bd->tcache_ptr; - emit_move_r_imm32(SHR_PC, bd->addr); - rcache_flush(); - emith_jump(sh2_drc_dispatcher); - tcache_ptr = tmp; + bl_unresolved = unresolved_links[tcache_id]; - bd->addr = 0; - return bd->tcache_ptr; -} + // remove from hash table, make incoming links unresolved + // XXX: maybe patch branches w/flush instead? + for (i = 0; i < bd->entry_count; i++) { + rm_from_hashlist(&bd->entryp[i], tcache_id); -static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask) -{ - //block_link *bl = block_links[tcache_id]; - //int bl_count = block_link_counts[tcache_id]; - block_desc *btab = block_tables[tcache_id]; - u16 *p = drc_ram_blk + ((a & mask) >> shift); - u16 *pmax = drc_ram_blk + (mask >> shift); - void *tcache_min, *tcache_max; - int zeros; - u16 *pt; - - // Figure out what the main block is, as subblocks also have the flag set. - // This relies on sub having single entry. It's possible that innocent - // block might be hit, but that's not such a big deal. - if ((p[0] >> 1) != (p[1] >> 1)) { - for (; p > drc_ram_blk; p--) - if (p[-1] == 0 || (p[-1] >> 1) == (*p >> 1)) - break; - } - pt = p; + // since we never reuse tcache space of dead blocks, + // insert jump to dispatcher for blocks that are linked to this + tcache_ptr = bd->entryp[i].tcache_ptr; + emit_move_r_imm32(SHR_PC, bd->addr); + rcache_flush(); + emith_jump(sh2_drc_dispatcher); - for (; p > drc_ram_blk; p--) - if ((*p & 1)) - break; + host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr); - if (!(*p & 1)) { - dbg(1, "smc rm: missing block start for %08x?", a); - p = pt; + for (bl = bd->entryp[i].links; bl != NULL; ) { + bl_next = bl->next; + bl->next = bl_unresolved; + bl_unresolved = bl; + bl = bl_next; + } } - if (*p == 0) - return; + tcache_ptr = tmp; + unresolved_links[tcache_id] = bl_unresolved; - tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id); - *p = 0; + bd->addr = bd->end_addr = 0; + bd->entry_count = 0; +} - for (p++, zeros = 0; p < pmax && zeros < MAX_LITERAL_OFFSET / 2; p++) { - int id = *p >> 1; - if (id == 0) { - // there can be holes because games sometimes keep variables - // directly in literal pool and we don't inline them to avoid recompile - // (Star Wars Arcade) - zeros++; +static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask) +{ + struct block_list **blist = NULL, *entry; + u32 from = ~0, to = 0; + struct block_desc *block; + + blist = &inval_lookup[tcache_id][(a & mask) / ADDR_TO_BLOCK_PAGE]; + entry = *blist; + while (entry != NULL) { + block = entry->block; + if (block->addr <= a && a < block->end_addr) { + if (block->addr < from) + from = block->addr; + if (block->end_addr > to) + to = block->end_addr; + + sh2_smc_rm_block_entry(block, tcache_id, mask); + + // entry lost, restart search + entry = *blist; continue; } - if (*p & 1) { - if (id == (p[1] >> 1)) - // hit other block - break; - tcache_max = sh2_smc_rm_block_entry(&btab[id], tcache_id); - } - *p = 0; + entry = entry->next; } - host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4*4 + 4)); + // clear entry points + if (from < to) { + u16 *p = drc_ram_blk + ((from & mask) >> shift); + memset(p, 0, (to - from) >> (shift - 1)); + } } void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) @@ -3021,7 +3058,7 @@ void block_stats(void) total += block_tables[b][i].refcount; for (c = 0; c < 10; c++) { - block_desc *blk, *maxb = NULL; + struct block_desc *blk, *maxb = NULL; int max = 0; for (b = 0; b < ARRAY_SIZE(block_tables); b++) { for (i = 0; i < block_counts[b]; i++) { @@ -3075,12 +3112,22 @@ int sh2_drc_init(SH2 *sh2) if (block_tables[i] == NULL) goto fail; // max 2 block links (exits) per block - block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0])); - if (block_links[i] == NULL) + block_link_pool[i] = calloc(block_link_pool_max_counts[i], + sizeof(*block_link_pool[0])); + if (block_link_pool[i] == NULL) + goto fail; + + inval_lookup[i] = calloc(ram_sizes[i] / ADDR_TO_BLOCK_PAGE, + sizeof(inval_lookup[0])); + if (inval_lookup[i] == NULL) + goto fail; + + hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0])); + if (hash_tables[i] == NULL) goto fail; } memset(block_counts, 0, sizeof(block_counts)); - memset(block_link_counts, 0, sizeof(block_link_counts)); + memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts)); drc_cmn_init(); tcache_ptr = tcache; @@ -3106,12 +3153,6 @@ int sh2_drc_init(SH2 *sh2) #endif } - if (hash_table == NULL) { - hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); - if (hash_table == NULL) - goto fail; - } - return 0; fail: @@ -3123,32 +3164,123 @@ void sh2_drc_finish(SH2 *sh2) { int i; - if (block_tables[0] != NULL) { - block_stats(); + if (block_tables[0] == NULL) + return; - for (i = 0; i < TCACHE_BUFFERS; i++) { + sh2_drc_flush_all(); + + for (i = 0; i < TCACHE_BUFFERS; i++) { #if (DRC_DEBUG & 4) - printf("~~~ tcache %d\n", i); - tcache_dsm_ptrs[i] = tcache_bases[i]; - tcache_ptr = tcache_ptrs[i]; - do_host_disasm(i); + printf("~~~ tcache %d\n", i); + tcache_dsm_ptrs[i] = tcache_bases[i]; + tcache_ptr = tcache_ptrs[i]; + do_host_disasm(i); #endif - if (block_tables[i] != NULL) - free(block_tables[i]); - block_tables[i] = NULL; - if (block_links[i] == NULL) - free(block_links[i]); - block_links[i] = NULL; + if (block_tables[i] != NULL) + free(block_tables[i]); + block_tables[i] = NULL; + if (block_link_pool[i] == NULL) + free(block_link_pool[i]); + block_link_pool[i] = NULL; + + if (inval_lookup[i] == NULL) + free(inval_lookup[i]); + inval_lookup[i] = NULL; + + if (hash_tables[i] != NULL) { + free(hash_tables[i]); + hash_tables[i] = NULL; } + } + + drc_cmn_cleanup(); +} + +#endif /* DRC_SH2 */ + +static void *dr_get_pc_base(u32 pc, int is_slave) +{ + void *ret = NULL; + u32 mask = 0; - drc_cmn_cleanup(); + if ((pc & ~0x7ff) == 0) { + // BIOS + ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m; + mask = 0x7ff; + } + else if ((pc & 0xfffff000) == 0xc0000000) { + // data array + ret = Pico32xMem->data_array[is_slave]; + mask = 0xfff; + } + else if ((pc & 0xc6000000) == 0x06000000) { + // SDRAM + ret = Pico32xMem->sdram; + mask = 0x03ffff; + } + else if ((pc & 0xc6000000) == 0x02000000) { + // ROM + ret = Pico.rom; + mask = 0x3fffff; } - if (hash_table != NULL) { - free(hash_table); - hash_table = NULL; + if (ret == NULL) + return (void *)-1; // NULL is valid value + + return (char *)ret - (pc & ~mask); +} + +void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc) +{ + u16 *dr_pc_base; + u32 pc, target, op; + int cycles; + + memset(op_flags, 0, BLOCK_INSN_LIMIT); + + dr_pc_base = dr_get_pc_base(base_pc, is_slave); + + for (cycles = 0, pc = base_pc; cycles < BLOCK_INSN_LIMIT-1; cycles++, pc += 2) { + op = FETCH_OP(pc); + if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR + signed int offs = ((signed int)(op << 20) >> 19); + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + target = pc + offs + 2; + if (base_pc <= target && target < base_pc + BLOCK_INSN_LIMIT * 2) + OP_FLAGS(target) |= OF_BTARGET; + break; + } + if ((op & 0xf000) == 0) { + op &= 0xff; + if (op == 0x1b) // SLEEP + break; + // BRAF, BSRF, RTS, RTE + if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + continue; + } + if ((op & 0xf0df) == 0x400b) { // JMP, JSR + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) + signed int offs = ((signed int)(op << 24) >> 23); + if (op & 0x0400) + OP_FLAGS(pc + 2) |= OF_DELAY_OP; + target = pc + offs + 4; + if (base_pc <= target && target < base_pc + BLOCK_INSN_LIMIT * 2) + OP_FLAGS(target) |= OF_BTARGET; + } + if ((op & 0xff00) == 0xc300) // TRAPA + break; } + *end_pc = pc; } -// vim:shiftwidth=2:expandtab +// vim:shiftwidth=2:ts=2:expandtab