X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu%2Fsh2%2Fcompiler.c;h=ee843641a34e9c9872bcad60079c498b37ac71b8;hb=e05b81fc5b3f640496795ced5d893ece4cc51c2d;hp=fc484135f1da7a63a3e947a2afaf91f78c8c3329;hpb=8b4f38f4c6977ff80fff0ec92228914fe930e534;p=picodrive.git diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index fc48413..ee84364 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -41,6 +41,16 @@ static char sh2dasm_buff[64]; #else #define do_host_disasm(x) #endif + +#if (DRC_DEBUG & 4) +static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr) +{ + if (block != NULL) + dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', + sh2->pc, block, (signed int)sr >> 12); + return block; +} +#endif // } debug #define BLOCK_CYCLE_LIMIT 100 @@ -101,7 +111,7 @@ static temp_reg_t reg_temp[] = { { 3, }, }; -#else +#elif defined(__i386__) #include "../drc/emit_x86.c" static const int reg_map_g2h[] = { @@ -121,6 +131,8 @@ static temp_reg_t reg_temp[] = { { xDX, }, }; +#else +#error unsupported arch #endif #define T 0x00000001 @@ -128,15 +140,17 @@ static temp_reg_t reg_temp[] = { #define I 0x000000f0 #define Q 0x00000100 #define M 0x00000200 +#define T_save 0x00000800 +#define I_SHIFT 4 #define Q_SHIFT 8 #define M_SHIFT 9 typedef struct block_desc_ { - u32 addr; // SH2 PC address - u32 end_addr; // TODO rm? - void *tcache_ptr; // translated block for above PC - struct block_desc_ *next; // next block with the same PC hash + u32 addr; // SH2 PC address + u32 end_addr; // TODO rm? + void *tcache_ptr; // translated block for above PC + struct block_desc_ *next; // next block with the same PC hash #if (DRC_DEBUG & 1) int refcount; #endif @@ -155,12 +169,19 @@ static int block_counts[3]; #define HASH_MASK (MAX_HASH_ENTRIES - 1) static void **hash_table; -static void REGPARM(2) (*sh2_drc_entry)(const void *block, SH2 *sh2); -static void (*sh2_drc_exit)(void); +#define HASH_FUNC(hash_tab, addr) \ + ((block_desc **)(hash_tab))[(addr) & HASH_MASK] + +static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2); +static void (*sh2_drc_dispatcher)(void); +static void (*sh2_drc_exit)(void); +static void (*sh2_drc_test_irq)(void); +static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d); +static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d); +static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d); +static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d); -// tmp extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); -static void REGPARM(1) sh2_test_irq(SH2 *sh2); static void flush_tcache(int tcid) { @@ -208,11 +229,29 @@ static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) *blk_id = *bcount; (*bcount)++; + if ((addr & 0xc6000000) == 0x02000000) { // ROM + bd->next = HASH_FUNC(hash_table, addr); + HASH_FUNC(hash_table, addr) = bd; +#if (DRC_DEBUG & 1) + if (bd->next != NULL) { + printf(" hash collision with %08x\n", bd->next->addr); + hash_collisions++; + } +#endif + } + return bd; } -#define HASH_FUNC(hash_tab, addr) \ - ((block_desc **)(hash_tab))[(addr) & HASH_MASK] +int find_in_array(u32 *array, size_t size, u32 what) +{ + size_t i; + for (i = 0; i < size; i++) + if (what == array[i]) + return i; + + return -1; +} // --------------------------------------------------------------- @@ -462,9 +501,14 @@ static int emit_memhandler_read(int size) emith_move_r_r(ctxr, CONTEXT_REG); switch (size) { case 0: // 8 + // must writeback cycles for poll detection stuff + if (reg_map_g2h[SHR_SR] != -1) + emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4); emith_call(p32x_sh2_read8); break; case 1: // 16 + if (reg_map_g2h[SHR_SR] != -1) + emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4); emith_call(p32x_sh2_read16); break; case 2: // 32 @@ -476,19 +520,32 @@ static int emit_memhandler_read(int size) return rcache_get_tmp_arg(0); } -static void emit_memhandler_write(int size) +static void emit_memhandler_write(int size, u32 pc, int delay) { int ctxr; host_arg2reg(ctxr, 2); - emith_move_r_r(ctxr, CONTEXT_REG); switch (size) { case 0: // 8 - emith_call(p32x_sh2_write8); + // XXX: consider inlining sh2_drc_write8 + if (delay) { + emith_call(sh2_drc_write8_slot); + } else { + emit_move_r_imm32(SHR_PC, pc); + rcache_clean(); + emith_call(sh2_drc_write8); + } break; case 1: // 16 - emith_call(p32x_sh2_write16); + if (delay) { + emith_call(sh2_drc_write16_slot); + } else { + emit_move_r_imm32(SHR_PC, pc); + rcache_clean(); + emith_call(sh2_drc_write16); + } break; case 2: // 32 + emith_move_r_r(ctxr, CONTEXT_REG); emith_call(p32x_sh2_write32); break; } @@ -506,19 +563,6 @@ static int emit_indirect_indexed_read(int rx, int ry, int size) return emit_memhandler_read(size); } -// tmp_wr -> @(Rx,Ry) -static void emit_indirect_indexed_write(int tmp_wr, int rx, int ry, int size) -{ - int a0, t; - rcache_clean(); - t = rcache_get_tmp_arg(1); - emith_move_r_r(t, tmp_wr); - a0 = rcache_get_reg_arg(0, rx); - t = rcache_get_reg(ry, RC_GR_READ); - emith_add_r_r(a0, t); - emit_memhandler_write(size); -} - // read @Rn, @rm static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size) { @@ -571,31 +615,86 @@ static void emit_do_static_regs(int is_write, int tmpr) } } -static void sh2_generate_utils(void) +static void emit_block_entry(void) { - int ctx, blk, tmp; + int arg0, arg1, arg2; - host_arg2reg(blk, 0); - host_arg2reg(ctx, 1); - host_arg2reg(tmp, 2); + host_arg2reg(arg0, 0); + host_arg2reg(arg1, 1); + host_arg2reg(arg2, 2); - // sh2_drc_entry(void *block, SH2 *sh2) - sh2_drc_entry = (void *)tcache_ptr; - emith_sh2_drc_entry(); - emith_move_r_r(CONTEXT_REG, ctx); // move ctx, arg1 - emit_do_static_regs(0, tmp); - emith_jump_reg(blk); // jump arg0 +#if (DRC_DEBUG & 4) + emith_move_r_r(arg1, CONTEXT_REG); + emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ)); + emith_call(sh2_drc_announce_entry); + rcache_invalidate(); +#endif + emith_tst_r_r(arg0, arg0); + EMITH_SJMP_START(DCOND_EQ); + emith_jump_reg_c(DCOND_NE, arg0); + EMITH_SJMP_END(DCOND_EQ); +} - // sh2_drc_exit(void) - sh2_drc_exit = (void *)tcache_ptr; - emit_do_static_regs(1, tmp); - emith_sh2_drc_exit(); +static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id) +{ + block_desc *bd = NULL; + void *block = NULL; + *tcache_id = 0; + + // we have full block id tables for data_array and RAM + // BIOS goes to data_array table too + if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) { + int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; + *tcache_id = 1 + is_slave; + if (blkid & 1) { + bd = &block_tables[*tcache_id][blkid >> 1]; + block = bd->tcache_ptr; + } + } + // RAM + else if ((pc & 0xc6000000) == 0x06000000) { + int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; + if (blkid & 1) { + bd = &block_tables[0][blkid >> 1]; + block = bd->tcache_ptr; + } + } + // ROM + else if ((pc & 0xc6000000) == 0x02000000) { + bd = HASH_FUNC(hash_table, pc); - rcache_invalidate(); + if (bd != NULL) { + if (bd->addr == pc) + block = bd->tcache_ptr; + else + block = dr_find_block(bd, pc); + } + } + +#if (DRC_DEBUG & 1) + if (bd != NULL) + bd->refcount++; +#endif + return block; } #define DELAYED_OP \ - delayed_op = 2 + drcf.delayed_op = 2 + +#define DELAY_SAVE_T(sr) { \ + emith_bic_r_imm(sr, T_save); \ + emith_tst_r_imm(sr, T); \ + EMITH_SJMP_START(DCOND_EQ); \ + emith_or_r_imm_c(DCOND_NE, sr, T_save); \ + EMITH_SJMP_END(DCOND_EQ); \ + drcf.use_saved_t = 1; \ +} + +#define FLUSH_CYCLES(sr) \ + if (cycles > 0) { \ + emith_sub_r_imm(sr, cycles << 12); \ + cycles = 0; \ + } #define CHECK_UNHANDLED_BITS(mask) { \ if ((op & (mask)) != 0) \ @@ -614,58 +713,162 @@ static void sh2_generate_utils(void) if (GET_Fx() >= n) \ goto default_ -static void *sh2_translate(SH2 *sh2, block_desc *other_block) +#define MAX_LOCAL_BRANCHES 16 + +// op_flags: data from 1st pass +#define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2] +#define OF_DELAY_OP (1 << 0) + +static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id) { + // XXX: maybe use structs instead? + void *branch_target_ptr[MAX_LOCAL_BRANCHES]; + u32 branch_target_pc[MAX_LOCAL_BRANCHES]; + int branch_target_count = 0; + void *branch_patch_ptr[MAX_LOCAL_BRANCHES]; + u32 branch_patch_pc[MAX_LOCAL_BRANCHES]; + int branch_patch_count = 0; + int branch_patch_cond = -1; + u8 op_flags[BLOCK_CYCLE_LIMIT + 1]; + struct { + u32 delayed_op:2; + u32 test_irq:1; + u32 use_saved_t:1; // delayed op modifies T + } drcf = { 0, }; + void *block_entry; block_desc *this_block; - unsigned int pc = sh2->pc; - int op, delayed_op = 0, test_irq = 0; - int tcache_id = 0, blkid = 0; - int cycles = 0; - u32 tmp, tmp2, tmp3, tmp4, sr; + u32 pc, base_pc, end_pc; // PC of current, first, last insn + int blkid_main = 0; + u32 tmp, tmp2; + int cycles; + int op; + int i; + + base_pc = sh2->pc; // validate PC - tmp = sh2->pc >> 29; - if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { - printf("invalid PC, aborting: %08x\n", sh2->pc); + tmp = base_pc >> 29; + if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) { + printf("invalid PC, aborting: %08x\n", base_pc); // FIXME: be less destructive exit(1); } - if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { - // data_array, BIOS have separate tcache (shared) - tcache_id = 1 + sh2->is_slave; - } - tcache_ptr = tcache_ptrs[tcache_id]; - this_block = dr_add_block(pc, tcache_id, &blkid); + this_block = dr_add_block(base_pc, tcache_id, &blkid_main); + // predict tcache overflow tmp = tcache_ptr - tcache_bases[tcache_id]; - if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { - flush_tcache(tcache_id); - tcache_ptr = tcache_ptrs[tcache_id]; - other_block = NULL; // also gone too due to flush - this_block = dr_add_block(pc, tcache_id, &blkid); + if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) + return NULL; + + block_entry = tcache_ptr; + dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', + tcache_id, blkid_main, base_pc, block_entry); + + // 1st pass: scan forward for local branches + memset(op_flags, 0, sizeof(op_flags)); + for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) { + op = p32x_sh2_read16(pc, sh2); + if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + if ((op & 0xf000) == 0) { + op &= 0xff; + if (op == 0x23 || op == 0x03 || op == 0x0b) { // BRAF, BSRF, RTS + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + continue; + } + if ((op & 0xf0df) == 0x400b) { // JMP, JSR + pc += 2; + OP_FLAGS(pc) |= OF_DELAY_OP; + break; + } + if ((op & 0xf900) == 0x8900) { // BT(S), BF(S) + signed int offs = ((signed int)(op << 24) >> 23); + if (op & 0x0400) + OP_FLAGS(pc + 2) |= OF_DELAY_OP; + branch_target_pc[branch_target_count++] = pc + offs + 4; + if (branch_target_count == MAX_LOCAL_BRANCHES) { + printf("warning: branch target overflow\n"); + // will only spawn additional blocks + break; + } + } } - this_block->next = other_block; - if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM - HASH_FUNC(hash_table, pc) = this_block; + end_pc = pc; - block_entry = tcache_ptr; -#if (DRC_DEBUG & 1) - printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', - tcache_id, block_counts[tcache_id], pc, block_entry); - if (other_block != NULL) { - printf(" hash collision with %08x\n", other_block->addr); - hash_collisions++; + // clean branch_targets that are not really local, + // and that land on delay slots + for (i = 0, tmp = 0; i < branch_target_count; i++) { + pc = branch_target_pc[i]; + if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP)) + branch_target_pc[tmp++] = branch_target_pc[i]; } -#endif + branch_target_count = tmp; + memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count); - while (cycles < BLOCK_CYCLE_LIMIT || delayed_op) + // ------------------------------------------------- + // 2nd pass: actual compilation + pc = base_pc; + for (cycles = 0; pc <= end_pc || drcf.delayed_op; ) { - if (delayed_op > 0) - delayed_op--; + u32 tmp3, tmp4, sr; + + if (drcf.delayed_op > 0) + drcf.delayed_op--; + + i = find_in_array(branch_target_pc, branch_target_count, pc); + if (i >= 0) + { + if (pc != sh2->pc) + { + /* make "subblock" - just a mid-block entry */ + block_desc *subblock; + u16 *drcblk; + int blkid; + + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + FLUSH_CYCLES(sr); + rcache_flush(); + do_host_disasm(tcache_id); + + subblock = dr_add_block(pc, tcache_id, &blkid); + if (subblock == NULL) + return NULL; + subblock->end_addr = pc; + + if (tcache_id != 0) { // data array, BIOS + drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; + drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT; + *drcblk = (blkid << 1) | 1; + } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM + drcblk = Pico32xMem->drcblk_ram; + drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; + *drcblk = (blkid << 1) | 1; + } + + dbg(1, "=== %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm', + tcache_id, blkid, pc, tcache_ptr); + } + branch_target_ptr[i] = tcache_ptr; + + // must update PC + emit_move_r_imm32(SHR_PC, pc); + rcache_clean(); + + // check cycles + sr = rcache_get_reg(SHR_SR, RC_GR_READ); + emith_cmp_r_imm(sr, 0); + emith_jump_cond(DCOND_LE, sh2_drc_exit); + } op = p32x_sh2_read16(pc, sh2); @@ -705,26 +908,34 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp3 = rcache_get_reg(tmp2, RC_GR_READ); emith_move_r_r(tmp, tmp3); if (tmp2 == SHR_SR) - emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0 + emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0 goto end_op; case 0x03: CHECK_UNHANDLED_BITS(0xd0); // BRAF Rm 0000mmmm00100011 // BSRF Rm 0000mmmm00000011 DELAYED_OP; - if (!(op & 0x20)) - emit_move_r_imm32(SHR_PR, pc + 2); - tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE); + tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); emith_move_r_r(tmp, tmp2); - emith_add_r_imm(tmp, pc + 2); + if (op & 0x20) + emith_add_r_imm(tmp, pc + 2); + else { // BSRF + tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE); + emith_move_r_imm(tmp3, pc + 2); + emith_add_r_r(tmp, tmp3); + } cycles++; goto end_op; case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 - tmp = rcache_get_reg(GET_Rm(), RC_GR_READ); - emit_indirect_indexed_write(tmp, SHR_R0, GET_Rn(), op & 3); + rcache_clean(); + tmp = rcache_get_reg_arg(1, GET_Rm()); + tmp2 = rcache_get_reg_arg(0, SHR_R0); + tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ); + emith_add_r_r(tmp2, tmp3); + emit_memhandler_write(op & 3, pc, drcf.delayed_op); goto end_op; case 0x07: // MUL.L Rm,Rn 0000nnnnmmmm0111 @@ -740,10 +951,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) { case 0: // CLRT 0000000000001000 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); break; case 1: // SETT 0000000000011000 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_or_r_imm(sr, T); break; case 2: // CLRMAC 0000000000101000 @@ -765,6 +980,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 1: // DIV0U 0000000000011001 CHECK_UNHANDLED_BITS(0xf00); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, M|Q|T); break; case 2: // MOVT Rn 0000nnnn00101001 @@ -801,23 +1018,22 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) { case 0: // RTS 0000000000001011 DELAYED_OP; - emit_move_r_r(SHR_PPC, SHR_PR); + emit_move_r_r(SHR_PC, SHR_PR); cycles++; break; case 1: // SLEEP 0000000000011011 emit_move_r_imm32(SHR_PC, pc - 2); tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); emith_clear_msb(tmp, tmp, 20); // clear cycles - test_irq = 1; cycles = 1; - break; + goto end_op; case 2: // RTE 0000000000101011 DELAYED_OP; rcache_clean(); // pop PC rcache_get_reg_arg(0, SHR_SP); tmp = emit_memhandler_read(2); - tmp2 = rcache_get_reg(SHR_PPC, RC_GR_WRITE); + tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE); emith_move_r_r(tmp2, tmp); rcache_free_tmp(tmp); rcache_clean(); @@ -825,11 +1041,12 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_reg_arg(0, SHR_SP); emith_add_r_imm(tmp, 4); tmp = emit_memhandler_read(2); - emith_write_sr(tmp); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_write_sr(sr, tmp); rcache_free_tmp(tmp); tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); emith_add_r_imm(tmp, 4*2); - test_irq = 1; + drcf.test_irq = 1; cycles += 3; break; default: @@ -889,7 +1106,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_reg_arg(0, GET_Rn()); tmp2 = rcache_get_reg_arg(1, GET_Rm()); emith_add_r_imm(tmp, (op & 0x0f) * 4); - emit_memhandler_write(2); + emit_memhandler_write(2, pc, drcf.delayed_op); goto end_op; case 0x02: @@ -901,7 +1118,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(1, GET_Rm()); - emit_memhandler_write(op & 3); + emit_memhandler_write(op & 3, pc, drcf.delayed_op); goto end_op; case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101 @@ -911,12 +1128,14 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) rcache_clean(); rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(1, GET_Rm()); - emit_memhandler_write(op & 3); + emit_memhandler_write(op & 3, pc, drcf.delayed_op); goto end_op; case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, M|Q|T); emith_tst_r_imm(tmp2, (1<<31)); EMITH_SJMP_START(DCOND_EQ); @@ -935,6 +1154,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) sr = rcache_get_reg(SHR_SR, RC_GR_RMW); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_tst_r_r(tmp2, tmp3); emit_or_t_if_eq(sr); @@ -960,6 +1181,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); emith_eor_r_r_r(tmp, tmp2, tmp3); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_tst_r_imm(tmp, 0x000000ff); emit_or_t_if_eq(tmp); @@ -1011,6 +1234,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) sr = rcache_get_reg(SHR_SR, RC_GR_RMW); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_cmp_r_r(tmp2, tmp3); switch (op & 0x07) @@ -1051,6 +1276,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 0); emith_adcf_r_r(tmp2, tmp2); emith_tpush_carry(sr, 0); // keep Q1 in T for now @@ -1061,16 +1288,16 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) // add or sub, invert T if carry to get Q1 ^ Q2 // in: (Q ^ M) passed in Q, Q1 in T emith_sh2_div1_step(tmp2, tmp3, sr); - emith_bic_r_imm(sr, Q); - emith_tst_r_imm(sr, M); - EMITH_SJMP_START(DCOND_EQ); - emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M - EMITH_SJMP_END(DCOND_EQ); - emith_tst_r_imm(sr, T); - EMITH_SJMP_START(DCOND_EQ); - emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 - EMITH_SJMP_END(DCOND_EQ); - emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) + emith_bic_r_imm(sr, Q); + emith_tst_r_imm(sr, M); + EMITH_SJMP_START(DCOND_EQ); + emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M + EMITH_SJMP_END(DCOND_EQ); + emith_tst_r_imm(sr, T); + EMITH_SJMP_START(DCOND_EQ); + emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2 + EMITH_SJMP_END(DCOND_EQ); + emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2) goto end_op; case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ); @@ -1093,6 +1320,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); if (op & 4) { // adc emith_tpop_carry(sr, 0); emith_adcf_r_r(tmp, tmp2); @@ -1108,6 +1337,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); if (op & 4) { emith_addf_r_r(tmp, tmp2); @@ -1138,6 +1369,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 2: // SHAL Rn 0100nnnn00100000 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 0); // dummy emith_lslf(tmp, tmp, 1); emith_tpush_carry(sr, 0); @@ -1149,6 +1382,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) } tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_subf_r_imm(tmp, 1); emit_or_t_if_eq(sr); @@ -1162,6 +1397,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 2: // SHAR Rn 0100nnnn00100001 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 0); // dummy if (op & 0x20) { emith_asrf(tmp, tmp, 1); @@ -1172,6 +1409,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 1: // CMP/PZ Rn 0100nnnn00010001 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_cmp_r_imm(tmp, 0); EMITH_SJMP_START(DCOND_LT); @@ -1211,8 +1450,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) rcache_get_reg_arg(0, GET_Rn()); tmp3 = rcache_get_reg_arg(1, tmp); if (tmp == SHR_SR) - emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0 - emit_memhandler_write(2); + emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0 + emit_memhandler_write(2, pc, drcf.delayed_op); goto end_op; case 0x04: case 0x05: @@ -1222,6 +1461,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 0x05: // ROTR Rn 0100nnnn00000101 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 0); // dummy if (op & 1) { emith_rorf(tmp, tmp, 1); @@ -1233,6 +1474,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 0x25: // ROTCR Rn 0100nnnn00100101 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 0); if (op & 1) { emith_rorcf(tmp); @@ -1243,6 +1486,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 0x15: // CMP/PL Rn 0100nnnn00010101 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_cmp_r_imm(tmp, 0); EMITH_SJMP_START(DCOND_LE); @@ -1280,8 +1525,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) rcache_get_reg_arg(0, GET_Rn()); tmp2 = emit_memhandler_read(2); if (tmp == SHR_SR) { - emith_write_sr(tmp2); - test_irq = 1; + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); + emith_write_sr(sr, tmp2); + drcf.test_irq = 1; } else { tmp = rcache_get_reg(tmp, RC_GR_WRITE); emith_move_r_r(tmp, tmp2); @@ -1343,7 +1591,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) DELAYED_OP; if (!(op & 0x20)) emit_move_r_imm32(SHR_PR, pc + 2); - emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f); + emit_move_r_r(SHR_PC, (op >> 8) & 0x0f); cycles++; break; case 1: // TAS.B @Rn 0100nnnn00011011 @@ -1352,6 +1600,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) rcache_get_reg_arg(0, GET_Rn()); tmp = emit_memhandler_read(0); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_cmp_r_imm(tmp, 0); emit_or_t_if_eq(sr); @@ -1361,7 +1611,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) emith_move_r_r(tmp2, tmp); rcache_free_tmp(tmp); rcache_get_reg_arg(0, GET_Rn()); - emit_memhandler_write(0); + emit_memhandler_write(0, pc, drcf.delayed_op); cycles += 3; break; default: @@ -1385,8 +1635,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) goto default_; } if (tmp2 == SHR_SR) { - emith_write_sr(tmp); - test_irq = 1; + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); + emith_write_sr(sr, tmp); + drcf.test_irq = 1; } else { tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE); emith_move_r_r(tmp2, tmp); @@ -1490,6 +1743,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) break; case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_tpop_carry(sr, 1); emith_negcf_r_r(tmp2, tmp); emith_tpush_carry(sr, 1); @@ -1535,7 +1790,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp2 = rcache_get_reg_arg(1, SHR_R0); tmp3 = (op & 0x100) >> 8; emith_add_r_imm(tmp, (op & 0x0f) << tmp3); - emit_memhandler_write(tmp3); + emit_memhandler_write(tmp3, pc, drcf.delayed_op); goto end_op; case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd @@ -1553,6 +1808,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_tmp(); tmp2 = rcache_get_reg(0, RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_move_r_imm_s8(tmp, op & 0xff); emith_bic_r_imm(sr, T); emith_cmp_r_r(tmp2, tmp); @@ -1570,11 +1827,19 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ; int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE; signed int offs = ((signed int)(op << 24) >> 23); - tmp = rcache_get_reg(delayed_op ? SHR_PPC : SHR_PC, RC_GR_WRITE); - emith_move_r_imm(tmp, pc + (delayed_op ? 2 : 0)); - emith_sh2_test_t(); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (find_in_array(branch_target_pc, branch_target_count, pc + offs + 2) >= 0) { + branch_patch_pc[branch_patch_count] = pc + offs + 2; + branch_patch_cond = insn_cond; + goto end_op; + } + + // can't resolve branch, cause end of block + tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE); + emith_move_r_imm(tmp, pc + (drcf.delayed_op ? 2 : 0)); + emith_tst_r_imm(sr, T); EMITH_SJMP_START(jmp_cond); - if (!delayed_op) + if (!drcf.delayed_op) offs += 2; if (offs < 0) { emith_sub_r_imm_c(insn_cond, tmp, -offs); @@ -1582,7 +1847,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) emith_add_r_imm_c(insn_cond, tmp, offs); EMITH_SJMP_END(jmp_cond); cycles += 2; - if (!delayed_op) + if (!drcf.delayed_op) goto end_block_btf; goto end_op; }} @@ -1606,7 +1871,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) DELAYED_OP; do_bra: tmp = ((signed int)(op << 20) >> 19); - emit_move_r_imm32(SHR_PPC, pc + tmp + 2); + emit_move_r_imm32(SHR_PC, pc + tmp + 2); cycles++; break; @@ -1629,7 +1894,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp2 = rcache_get_reg_arg(1, SHR_R0); tmp3 = (op & 0x300) >> 8; emith_add_r_imm(tmp, (op & 0xff) << tmp3); - emit_memhandler_write(tmp3); + emit_memhandler_write(tmp3, pc, drcf.delayed_op); goto end_op; case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd @@ -1654,13 +1919,13 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp = rcache_get_reg_arg(0, SHR_SP); emith_add_r_imm(tmp, 4); tmp = rcache_get_reg_arg(1, SHR_SR); - emith_clear_msb(tmp, tmp, 20); - emit_memhandler_write(2); + emith_clear_msb(tmp, tmp, 22); + emit_memhandler_write(2, pc, drcf.delayed_op); // push PC rcache_get_reg_arg(0, SHR_SP); tmp = rcache_get_tmp_arg(1); emith_move_r_imm(tmp, pc); - emit_memhandler_write(2); + emit_memhandler_write(2, pc, drcf.delayed_op); // obtain new PC tmp = rcache_get_reg_arg(0, SHR_VBR); emith_add_r_imm(tmp, (op & 0xff) * 4); @@ -1676,6 +1941,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 0x0800: // TST #imm,R0 11001000iiiiiiii tmp = rcache_get_reg(SHR_R0, RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_tst_r_imm(tmp, op & 0xff); emit_or_t_if_eq(sr); @@ -1695,6 +1962,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + if (drcf.delayed_op) + DELAY_SAVE_T(sr); emith_bic_r_imm(sr, T); emith_tst_r_imm(tmp, op & 0xff); emit_or_t_if_eq(sr); @@ -1719,7 +1988,7 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) tmp3 = rcache_get_reg_arg(0, SHR_GBR); tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ); emith_add_r_r(tmp3, tmp4); - emit_memhandler_write(0); + emit_memhandler_write(0, pc, drcf.delayed_op); cycles += 2; goto end_op; } @@ -1759,58 +2028,101 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) } end_op: - if (delayed_op == 1) - emit_move_r_r(SHR_PC, SHR_PPC); + // block-local conditional branch handling (with/without delay) + if (branch_patch_cond != -1 && drcf.delayed_op != 2) { + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + // handle cycles + FLUSH_CYCLES(sr); + rcache_clean(); - if (test_irq && delayed_op != 2) { - if (!delayed_op) + if (drcf.use_saved_t) + emith_tst_r_imm(sr, T_save); + else + emith_tst_r_imm(sr, T); + branch_patch_ptr[branch_patch_count] = tcache_ptr; + emith_jump_patchable(branch_patch_cond); + + drcf.use_saved_t = 0; + branch_patch_cond = -1; + branch_patch_count++; + drcf.delayed_op = 0; // XXX: delayed_op ends block, so must override + if (branch_patch_count == MAX_LOCAL_BRANCHES) { + printf("too many local branches\n"); + break; + } + } + // test irq? + // XXX: delay slots.. + if (drcf.test_irq && drcf.delayed_op != 2) { + if (!drcf.delayed_op) emit_move_r_imm32(SHR_PC, pc); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + FLUSH_CYCLES(sr); rcache_flush(); - emith_pass_arg_r(0, CONTEXT_REG); - emith_call(sh2_test_irq); - goto end_block_btf; + emith_call(sh2_drc_test_irq); + drcf.test_irq = 0; } - if (delayed_op == 1) + if (drcf.delayed_op == 1) break; do_host_disasm(tcache_id); } // delayed_op means some kind of branch - PC already handled - if (!delayed_op) + if (!drcf.delayed_op) emit_move_r_imm32(SHR_PC, pc); end_block_btf: this_block->end_addr = pc; + tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); + FLUSH_CYCLES(tmp); + rcache_flush(); + emith_jump(sh2_drc_dispatcher); + + // link local branches + for (i = 0; i < branch_patch_count; i++) { + void *target; + int t; + //printf("patch %08x %p\n", branch_patch_pc[i], branch_patch_ptr[i]); + t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]); + if (branch_target_ptr[t] != NULL) + target = branch_target_ptr[t]; + else { + // flush pc and go back to dispatcher (for now) + printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr); + target = tcache_ptr; + emit_move_r_imm32(SHR_PC, branch_patch_pc[i]); + rcache_flush(); + emith_jump(sh2_drc_dispatcher); + } + emith_jump_patch(branch_patch_ptr[i], target); + } + // mark memory blocks as containing compiled code - if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { + if (tcache_id != 0) { // data array, BIOS u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; - tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; + tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; - Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; + drcblk[tmp] = (blkid_main << 1) | 1; for (++tmp; tmp < tmp2; tmp++) { if (drcblk[tmp]) - break; // dont overwrite overlay block - drcblk[tmp] = blkid << 1; + continue; // dont overwrite overlay block(s) + drcblk[tmp] = blkid_main << 1; } } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM - tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; + tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; - Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; + Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1; for (++tmp; tmp < tmp2; tmp++) { if (Pico32xMem->drcblk_ram[tmp]) - break; - Pico32xMem->drcblk_ram[tmp] = blkid << 1; + continue; + Pico32xMem->drcblk_ram[tmp] = blkid_main << 1; } } - tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); - emith_sub_r_imm(tmp, cycles << 12); - rcache_flush(); - emith_jump(sh2_drc_exit); tcache_ptrs[tcache_id] = tcache_ptr; #ifdef ARM @@ -1824,6 +2136,13 @@ end_block_btf: insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); +/* + printf("~~~\n"); + tcache_dsm_ptrs[tcache_id] = block_entry; + do_host_disasm(tcache_id); + printf("~~~\n"); +*/ + #if (DRC_DEBUG & 2) fflush(stdout); #endif @@ -1837,59 +2156,165 @@ unimplemented: */ } -void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) +static void sh2_generate_utils(void) { - // TODO: need to handle self-caused interrupts - sh2_test_irq(sh2); + int arg0, arg1, arg2, sr, tmp; + void *sh2_drc_write_end, *sh2_drc_write_slot_end; - while (((signed int)sh2->sr >> 12) > 0) - { - void *block = NULL; - block_desc *bd = NULL; - - // FIXME: must avoid doing it so often.. - //sh2_test_irq(sh2); - - // we have full block id tables for data_array and RAM - // BIOS goes to data_array table too - if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { - int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; - if (blkid & 1) { - bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; - block = bd->tcache_ptr; - } - } - // RAM - else if ((sh2->pc & 0xc6000000) == 0x06000000) { - int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; - if (blkid & 1) { - bd = &block_tables[0][blkid >> 1]; - block = bd->tcache_ptr; - } - } - // ROM - else if ((sh2->pc & 0xc6000000) == 0x02000000) { - bd = HASH_FUNC(hash_table, sh2->pc); - - if (bd != NULL) { - if (bd->addr == sh2->pc) - block = bd->tcache_ptr; - else - block = dr_find_block(bd, sh2->pc); - } - } + host_arg2reg(arg0, 0); + host_arg2reg(arg1, 1); + host_arg2reg(arg2, 2); + emith_move_r_r(arg0, arg0); // nop - if (block == NULL) - block = sh2_translate(sh2, bd); + // sh2_drc_exit(void) + sh2_drc_exit = (void *)tcache_ptr; + emit_do_static_regs(1, arg2); + emith_sh2_drc_exit(); - dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', - sh2->pc, block, (signed int)sh2->sr >> 12); -#if (DRC_DEBUG & 1) - if (bd != NULL) - bd->refcount++; + // sh2_drc_dispatcher(void) + sh2_drc_dispatcher = (void *)tcache_ptr; + sr = rcache_get_reg(SHR_SR, RC_GR_READ); + emith_cmp_r_imm(sr, 0); + emith_jump_cond(DCOND_LT, sh2_drc_exit); + rcache_invalidate(); + emith_ctx_read(arg0, SHR_PC * 4); + emith_ctx_read(arg1, offsetof(SH2, is_slave)); + emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp)); + emith_call(lookup_block); + emit_block_entry(); + // lookup failed, call sh2_translate() + emith_move_r_r(arg0, CONTEXT_REG); + emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id + emith_call(sh2_translate); + emit_block_entry(); + // sh2_translate() failed, flush cache and retry + emith_ctx_read(arg0, offsetof(SH2, drc_tmp)); + emith_call(flush_tcache); + emith_move_r_r(arg0, CONTEXT_REG); + emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); + emith_call(sh2_translate); + emit_block_entry(); + // XXX: can't translate, fail + emith_call(exit); + + // sh2_drc_test_irq(void) + // assumes it's called from main function (may jump to dispatcher) + sh2_drc_test_irq = (void *)tcache_ptr; + emith_ctx_read(arg1, offsetof(SH2, pending_level)); + sr = rcache_get_reg(SHR_SR, RC_GR_READ); + emith_lsr(arg0, sr, I_SHIFT); + emith_and_r_imm(arg0, 0x0f); + emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)? + EMITH_SJMP_START(DCOND_GT); + emith_ret_c(DCOND_LE); // nope, return + EMITH_SJMP_END(DCOND_GT); + // adjust SP + tmp = rcache_get_reg(SHR_SP, RC_GR_RMW); + emith_sub_r_imm(tmp, 4*2); + rcache_clean(); + // push SR + tmp = rcache_get_reg_arg(0, SHR_SP); + emith_add_r_imm(tmp, 4); + tmp = rcache_get_reg_arg(1, SHR_SR); + emith_clear_msb(tmp, tmp, 22); + emith_move_r_r(arg2, CONTEXT_REG); + emith_call(p32x_sh2_write32); + rcache_invalidate(); + // push PC + rcache_get_reg_arg(0, SHR_SP); + emith_ctx_read(arg1, SHR_PC * 4); + emith_move_r_r(arg2, CONTEXT_REG); + emith_call(p32x_sh2_write32); + rcache_invalidate(); + // update I, cycles, do callback + emith_ctx_read(arg1, offsetof(SH2, pending_level)); + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_bic_r_imm(sr, I); + emith_or_r_r_lsl(sr, arg1, I_SHIFT); + emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles + rcache_flush(); + emith_move_r_r(arg0, CONTEXT_REG); + emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level); + // obtain new PC + emith_lsl(arg0, arg0, 2); + emith_ctx_read(arg1, SHR_VBR * 4); + emith_add_r_r(arg0, arg1); + emit_memhandler_read(2); + emith_ctx_write(arg0, SHR_PC * 4); +#ifdef __i386__ + emith_add_r_imm(xSP, 4); // fix stack +#endif + emith_jump(sh2_drc_dispatcher); + rcache_invalidate(); + + // sh2_drc_entry(SH2 *sh2) + sh2_drc_entry = (void *)tcache_ptr; + emith_sh2_drc_entry(); + emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0 + emit_do_static_regs(0, arg2); + emith_call(sh2_drc_test_irq); + emith_jump(sh2_drc_dispatcher); + + // write-caused irq detection + sh2_drc_write_end = tcache_ptr; + emith_tst_r_r(arg0, arg0); + EMITH_SJMP_START(DCOND_NE); + emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return + EMITH_SJMP_END(DCOND_NE); + // since PC is up to date, jump to it's block instead of returning + emith_call(sh2_drc_test_irq); + emith_jump_ctx(offsetof(SH2, drc_tmp)); + + // write-caused irq detection for writes in delay slot + sh2_drc_write_slot_end = tcache_ptr; + emith_tst_r_r(arg0, arg0); + EMITH_SJMP_START(DCOND_NE); + emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); + EMITH_SJMP_END(DCOND_NE); + // just burn cycles to get back to dispatcher after branch is handled + sr = rcache_get_reg(SHR_SR, RC_GR_RMW); + emith_ctx_write(sr, offsetof(SH2, irq_cycles)); + emith_clear_msb(sr, sr, 20); // clear cycles + rcache_flush(); + emith_jump_ctx(offsetof(SH2, drc_tmp)); + + // sh2_drc_write8(u32 a, u32 d) + sh2_drc_write8 = (void *)tcache_ptr; + emith_ret_to_ctx(offsetof(SH2, drc_tmp)); + emith_ctx_read(arg2, offsetof(SH2, write8_tab)); + emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); + + // sh2_drc_write16(u32 a, u32 d) + sh2_drc_write16 = (void *)tcache_ptr; + emith_ret_to_ctx(offsetof(SH2, drc_tmp)); + emith_ctx_read(arg2, offsetof(SH2, write16_tab)); + emith_sh2_wcall(arg0, arg2, sh2_drc_write_end); + + // sh2_drc_write8_slot(u32 a, u32 d) + sh2_drc_write8_slot = (void *)tcache_ptr; + emith_ret_to_ctx(offsetof(SH2, drc_tmp)); + emith_ctx_read(arg2, offsetof(SH2, write8_tab)); + emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); + + // sh2_drc_write16_slot(u32 a, u32 d) + sh2_drc_write16_slot = (void *)tcache_ptr; + emith_ret_to_ctx(offsetof(SH2, drc_tmp)); + emith_ctx_read(arg2, offsetof(SH2, write16_tab)); + emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end); + + rcache_invalidate(); +#if (DRC_DEBUG & 2) + host_dasm_new_symbol(sh2_drc_entry); + host_dasm_new_symbol(sh2_drc_dispatcher); + host_dasm_new_symbol(sh2_drc_exit); + host_dasm_new_symbol(sh2_drc_test_irq); + host_dasm_new_symbol(sh2_drc_write_end); + host_dasm_new_symbol(sh2_drc_write_slot_end); + host_dasm_new_symbol(sh2_drc_write8); + host_dasm_new_symbol(sh2_drc_write8_slot); + host_dasm_new_symbol(sh2_drc_write16); + host_dasm_new_symbol(sh2_drc_write16_slot); #endif - sh2_drc_entry(block, sh2); - } } static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) @@ -1897,6 +2322,7 @@ static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) u16 id = *p >> 1; block_desc *bd = btab + id; + // FIXME: skip subblocks; do both directions dbg(1, " killing block %08x", bd->addr); bd->addr = bd->end_addr = 0; @@ -1936,31 +2362,25 @@ void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) void sh2_execute(SH2 *sh2c, int cycles) { + int ret_cycles; sh2 = sh2c; // XXX sh2c->cycles_aim += cycles; cycles = sh2c->cycles_aim - sh2c->cycles_done; // cycles are kept in SHR_SR unused bits (upper 20) + // bit19 contains T saved for delay slot + // others are usual SH2 flags sh2c->sr &= 0x3f3; sh2c->sr |= cycles << 12; - sh2_drc_dispatcher(sh2c); + sh2_drc_entry(sh2c); - sh2c->cycles_done += cycles - ((signed int)sh2c->sr >> 12); -} + // TODO: irq cycles + ret_cycles = (signed int)sh2c->sr >> 12; + if (ret_cycles > 0) + printf("warning: drc returned with cycles: %d\n", ret_cycles); -static void REGPARM(1) sh2_test_irq(SH2 *sh2) -{ - if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f)) - { - if (sh2->pending_irl > sh2->pending_int_irq) - sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2); - else { - sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector); - sh2->pending_int_irq = 0; // auto-clear - sh2->pending_level = sh2->pending_irl; - } - } + sh2c->cycles_done += cycles - ret_cycles; } #if (DRC_DEBUG & 1)