X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=cpu.h;h=7ce72db525b93f1da0d172274f28a2a191437462;hb=eb3668fc5dab138073cd4844208ac05b94086a4a;hp=bebe773ebf45357eac74eee6d75b3b6b55a3cd02;hpb=2823a4c8196a02da86ee180cf55586d4e8c91a2f;p=gpsp.git

diff --git a/cpu.h b/cpu.h
index bebe773..7ce72db 100644
--- a/cpu.h
+++ b/cpu.h
@@ -112,6 +112,7 @@ extern u32 last_instruction;
 u32 function_cc step_debug(u32 pc, u32 cycles);
 u32 execute_arm(u32 cycles);
 void raise_interrupt(irq_type irq_raised);
+void set_cpu_mode(cpu_mode_type new_mode);
 
 u32 function_cc execute_load_u8(u32 address);
 u32 function_cc execute_load_u16(u32 address);
@@ -133,19 +134,20 @@ s32 translate_block_arm(u32 pc, translation_region_type translation_region,
 s32 translate_block_thumb(u32 pc, translation_region_type translation_region,
  u32 smc_enable);
 
-#ifdef GP2X_BUILD
-#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5)
-#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2)
-#define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128 * 2)
-#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32)
-
-#else
+#ifdef PSP_BUILD
 
 #define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4)
 #define RAM_TRANSLATION_CACHE_SIZE (1024 * 384)
 #define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128)
 #define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024)
 
+#else
+
+#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5)
+#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2)
+#define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128 * 2)
+#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32)
+
 #endif
 
 extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];