X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=deps%2Flightning%2Finclude%2Flightning%2Fjit_arm.h;h=558f5535336ba2ba033f2f2638ff6e8552d40e5e;hb=e2fb1389dc12376acb84e4993ed3b08760257252;hp=81451f12aaf0d538557c32215e6a7e5e066253ac;hpb=0adc619b5a5705d16cc6caea64951776ababbb96;p=pcsx_rearmed.git

diff --git a/deps/lightning/include/lightning/jit_arm.h b/deps/lightning/include/lightning/jit_arm.h
index 81451f12..558f5535 100644
--- a/deps/lightning/include/lightning/jit_arm.h
+++ b/deps/lightning/include/lightning/jit_arm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2019  Free Software Foundation, Inc.
+ * Copyright (C) 2012-2023  Free Software Foundation, Inc.
  *
  * This file is part of GNU lightning.
  *
@@ -106,6 +106,9 @@ typedef enum {
 
 typedef struct {
     jit_uint32_t version	: 4;
+    /* this field originally was only used for the 'e' in armv5te.
+     * it can also be used to force hardware division, if setting
+     * version to 7, telling it is armv7r or better. */
     jit_uint32_t extend		: 1;
     /* only generate thumb instructions for thumb2 */
     jit_uint32_t thumb		: 1;
@@ -117,6 +120,69 @@ typedef struct {
      * due to some memory ordering constraint not being respected, so,
      * disable by default */
     jit_uint32_t ldrt_strt	: 1;
+    /* assume functions called never match jit instruction set?
+     * that is libc, gmp, mpfr, etc functions are in thumb mode and jit
+     * is in arm mode, or the reverse, what may cause a crash upon return
+     * of that function if generating jit for a relative jump.
+     */
+    jit_uint32_t exchange	: 1;
+    /* By default assume cannot load unaligned data.
+     * A3.2.1
+     * Unaligned data access
+     * An ARMv7 implementation must support unaligned data accesses by
+     * some load and store instructions, as Table A3-1 shows. Software
+     * can set the SCTLR.A bit to control whether a misaligned access by
+     * one of these instructions causes an Alignment fault Data Abort
+     *  exception.
+     * Table A3-1 Alignment requirements of load/store instructions
+     *                                   Result if check fails when
+     * Instructions   Alignment check    SCTLR.A is 0      SCTLR.A is 1
+     * LDRB, LDREXB,
+     * LDRBT, LDRSB,
+     * LDRSBT, STRB,
+     * STREXB, STRBT,
+     * SWPB, TBB       None              -             -
+     * LDRH, LDRHT,
+     * LDRSH, LDRSHT,
+     * STRH, STRHT,
+     * TBH             Halfword          Unaligned access  Alignment fault
+     * LDREXH, STREXH  Halfword          Alignment fault   Alignment fault
+     * LDR, LDRT,
+     * STR, STRT       Word              Unaligned access  Alignment fault
+     * LDREX, STREX    Word              Alignment fault   Alignment fault
+     * LDREXD, STREXD  Doubleword        Alignment fault   Alignment fault
+     * All forms of
+     * LDM and STM,
+     * LDRD, RFE, SRS,
+     * STRD, SWP        Word              Alignment fault   Alignment fault
+     * LDC, LDC2,
+     * STC, STC2        Word              Alignment fault   Alignment fault
+     * VLDM, VLDR,
+     * VPOP, VPUSH,
+     * VSTM, VSTR       Word              Alignment fault   Alignment fault
+     * VLD1, VLD2,
+     * VLD3, VLD4,
+     * VST1, VST2,
+     * VST3, VST4,
+     * all with
+     * standard
+     * alignment (a)    Element size      Unaligned access  Alignment fault
+     * VLD1, VLD2,
+     * VLD3, VLD4,
+     * VST1, VST2,
+     * VST3, VST4,
+     * all with
+     * @<align>
+     * specified (a)   As specified by    Alignment fault  Alignment fault
+     *                 @<align>
+     *
+     * (a) These element and structure load/store instructions are only in
+     * the Advanced SIMD Extension to the ARMv7 ARM and Thumb instruction
+     * sets. ARMv7 does not support the pre-ARMv6 alignment model, so
+     * software cannot use that model with these instructions.
+     */
+    jit_uint32_t unaligned	: 1;
+    jit_uint32_t vfp_unaligned	: 1;
 } jit_cpu_t;
 
 /*